From e985ae703948268ba9ee3127a7d8e5b5c188ce6e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 6 Oct 2022 20:37:36 +0200
Subject: simul: fix initial value of record signals

---
 src/simul/simul-vhdl_simul.adb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index 26c2179ea..e3b624971 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -262,9 +262,9 @@ package body Simul.Vhdl_Simul is
                end loop;
             end;
          when Type_Record =>
-            for I in Val.Typ.Rec.E'Range loop
+            for I in Target.Typ.Rec.E'Range loop
                declare
-                  E : Rec_El_Type renames Val.Typ.Rec.E (I);
+                  E : Rec_El_Type renames Target.Typ.Rec.E (I);
                   Smem : Memory_Ptr;
                begin
                   if Val.Mem = null then
-- 
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