From e4b637d67f7f6860fbaccc98798c1f55cfb190ff Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 8 Aug 2018 07:24:39 +0200
Subject: Add testcase for #613

---
 testsuite/gna/issue613/ent.vhdl     | 12 ++++++++++++
 testsuite/gna/issue613/t1.vhdl      |  8 ++++++++
 testsuite/gna/issue613/t2.vhdl      |  8 ++++++++
 testsuite/gna/issue613/testsuite.sh | 22 ++++++++++++++++++++++
 4 files changed, 50 insertions(+)
 create mode 100644 testsuite/gna/issue613/ent.vhdl
 create mode 100644 testsuite/gna/issue613/t1.vhdl
 create mode 100644 testsuite/gna/issue613/t2.vhdl
 create mode 100755 testsuite/gna/issue613/testsuite.sh

diff --git a/testsuite/gna/issue613/ent.vhdl b/testsuite/gna/issue613/ent.vhdl
new file mode 100644
index 000000000..202a2b9d0
--- /dev/null
+++ b/testsuite/gna/issue613/ent.vhdl
@@ -0,0 +1,12 @@
+entity ent is
+end entity;
+
+architecture a of ent is
+  constant SimulationTime_c  : time    := 10000 sec;
+begin
+  process begin
+    report "Hello world" severity note;
+    wait;
+  end process;
+end;
+
diff --git a/testsuite/gna/issue613/t1.vhdl b/testsuite/gna/issue613/t1.vhdl
new file mode 100644
index 000000000..1572a0532
--- /dev/null
+++ b/testsuite/gna/issue613/t1.vhdl
@@ -0,0 +1,8 @@
+entity t1 is
+end entity;
+
+architecture a of t1 is
+  constant SimulationTime_c  : time    := 0 fs;
+begin
+end;
+
diff --git a/testsuite/gna/issue613/t2.vhdl b/testsuite/gna/issue613/t2.vhdl
new file mode 100644
index 000000000..c976ac39a
--- /dev/null
+++ b/testsuite/gna/issue613/t2.vhdl
@@ -0,0 +1,8 @@
+entity t2 is
+end entity;
+
+architecture a of t2 is
+  constant SimulationTime_c  : time    := 0.0 ps;
+begin
+end;
+
diff --git a/testsuite/gna/issue613/testsuite.sh b/testsuite/gna/issue613/testsuite.sh
new file mode 100755
index 000000000..ad890e137
--- /dev/null
+++ b/testsuite/gna/issue613/testsuite.sh
@@ -0,0 +1,22 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+if ! $GHDL --help -a | grep -q time-resolution; then
+  echo "option --time-resolution not available"
+else
+    # Below the resolution
+    analyze_failure --time-resolution=min ent.vhdl
+    
+    # Zero physical literals are always allowed.
+    analyze --time-resolution=sec t1.vhdl
+    analyze --time-resolution=sec t2.vhdl
+
+    analyze ent.vhdl
+    elab_simulate --time-resolution=ms ent
+
+    elab_simulate --time-resolution=auto ent
+    clean
+fi
+
+echo "Test successful"
-- 
cgit v1.2.3