From e45c19474897208c723af863db0d3337bf44928b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 30 Jun 2021 06:43:56 +0200
Subject: synth: minor renaming in netlists-memories

---
 src/synth/netlists-memories.adb |  4 ++--
 src/synth/netlists-memories.ads | 15 ++++++++-------
 src/synth/synth-vhdl_insts.adb  |  2 +-
 3 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/synth/netlists-memories.adb b/src/synth/netlists-memories.adb
index 6c7505842..0b9853b83 100644
--- a/src/synth/netlists-memories.adb
+++ b/src/synth/netlists-memories.adb
@@ -2349,7 +2349,7 @@ package body Netlists.Memories is
       end case;
    end Is_Const_Input;
 
-   procedure Extract_Memories2 (Ctxt : Context_Acc; M : Module)
+   procedure Extract_Memories (Ctxt : Context_Acc; M : Module)
    is
       Dyns : Instance_Tables.Instance;
       Mems : Instance_Tables.Instance;
@@ -2445,7 +2445,7 @@ package body Netlists.Memories is
       end loop;
 
       Instance_Tables.Free (Mems);
-   end Extract_Memories2;
+   end Extract_Memories;
 
    --  Return True iff O is to MUX and any number of Dyn_Extract (possibly
    --  through mux2).
diff --git a/src/synth/netlists-memories.ads b/src/synth/netlists-memories.ads
index c7d891acf..eb704f224 100644
--- a/src/synth/netlists-memories.ads
+++ b/src/synth/netlists-memories.ads
@@ -19,19 +19,20 @@
 with Netlists.Builders; use Netlists.Builders;
 
 package Netlists.Memories is
-   --  Try to convert dyn_insert/dyn_extract to memory ports.
-   procedure Extract_Memories2 (Ctxt : Context_Acc; M : Module);
-
-   --  Count the number of memidx in a memory address.
-   function Count_Memidx (Addr : Net) return Natural;
-
    --  True iff a RAM can be infered from VAL (the input of an assignment).
    --  TODO: handle partial write (offset)
    --  TODO: directly check with assignment target.
    function Can_Infere_RAM (Val : Net; Prev_Val : Net) return Boolean;
 
-   --  Transform VAL to a RAM.
+   --  Pre-transform VAL to a RAM: try to merge Mux2 into the dyn_insert.
    function Infere_RAM
      (Ctxt : Context_Acc; Val : Net; Tail : Net; Clk : Net; En : Net)
       return Net;
+
+   --  Try to convert dyn_insert/dyn_extract to memory ports.
+   procedure Extract_Memories (Ctxt : Context_Acc; M : Module);
+
+   --  Count the number of memidx in a memory address.
+   function Count_Memidx (Addr : Net) return Natural;
+
 end Netlists.Memories;
diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb
index 679b63312..2902001d5 100644
--- a/src/synth/synth-vhdl_insts.adb
+++ b/src/synth/synth-vhdl_insts.adb
@@ -1728,7 +1728,7 @@ package body Synth.Vhdl_Insts is
       end if;
 
       if not Synth.Flags.Flag_Debug_Nomemory2 then
-         Netlists.Memories.Extract_Memories2 (Get_Build (Syn_Inst), Inst.M);
+         Netlists.Memories.Extract_Memories (Get_Build (Syn_Inst), Inst.M);
          --  Remove remaining clock edge gates.
          Netlists.Cleanup.Mark_And_Sweep (Inst.M);
       end if;
-- 
cgit v1.2.3