From dd6c67ac12d1371b4bc7b1a5570f9522d32a647a Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 30 Sep 2019 00:15:20 +0200
Subject: testsuite/synth: add a test for previous commit (dyn slice).

---
 testsuite/synth/mem02/ram4.vhdl    | 32 ++++++++++++++++++++++++
 testsuite/synth/mem02/tb_ram4.vhdl | 51 ++++++++++++++++++++++++++++++++++++++
 testsuite/synth/mem02/testsuite.sh |  2 +-
 3 files changed, 84 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/mem02/ram4.vhdl
 create mode 100644 testsuite/synth/mem02/tb_ram4.vhdl

diff --git a/testsuite/synth/mem02/ram4.vhdl b/testsuite/synth/mem02/ram4.vhdl
new file mode 100644
index 000000000..c397e44f1
--- /dev/null
+++ b/testsuite/synth/mem02/ram4.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram4 is
+  port (raddr : std_logic_vector (1 downto 0);
+        rdat : out std_logic_vector(1 downto 0);
+        rst : std_logic;
+        init : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end ram4;
+
+architecture behav of ram4 is
+  type rindx is record
+    idx : natural;
+  end record;
+
+  signal idx : rindx;
+  signal mem : std_logic_vector(7 downto 0);
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst = '1' then
+        mem <= init;
+      end if;
+      rdat <= mem((idx.idx+1) * 2 - 1 downto idx.idx * 2);
+    end if;
+  end process;
+
+  idx.idx <=to_integer(unsigned (raddr));
+end behav;
diff --git a/testsuite/synth/mem02/tb_ram4.vhdl b/testsuite/synth/mem02/tb_ram4.vhdl
new file mode 100644
index 000000000..4a109d14b
--- /dev/null
+++ b/testsuite/synth/mem02/tb_ram4.vhdl
@@ -0,0 +1,51 @@
+entity tb_ram4 is
+end tb_ram4;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram4 is
+  signal rdat : std_logic_vector(1 downto 0);
+  signal raddr : std_logic_vector(1 downto 0);
+  signal init : std_logic_vector(7 downto 0);
+  signal rst : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.ram4
+    port map (raddr => raddr, rdat => rdat, rst => rst, init => init,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    init <= b"01_11_00_10";
+    pulse;
+
+    rst <= '0';
+    init <= b"00_00_00_00";
+    raddr <= "00";
+    pulse;
+    assert rdat = "10" severity failure;
+
+    raddr <= "11";
+    pulse;
+    assert rdat = "01" severity failure;
+
+    raddr <= "01";
+    pulse;
+    assert rdat = "00" severity failure;
+
+    raddr <= "10";
+    pulse;
+    assert rdat = "11" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/testsuite.sh b/testsuite/synth/mem02/testsuite.sh
index 2d7da25bd..d212c22e3 100755
--- a/testsuite/synth/mem02/testsuite.sh
+++ b/testsuite/synth/mem02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in dpram1 ram3; do
+for t in dpram1 ram3 ram4; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
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