From d469d3bfe180707927a04a8d1e69a1276c88bb7c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 30 Sep 2019 20:32:13 +0200 Subject: synth-oper: implement >= and <= for uns/nat. Fix #952 --- src/synth/synth-oper.adb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index b9926aff0..ddb4b2e88 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -512,6 +512,9 @@ package body Synth.Oper is | Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Slv => -- "<=" (Unsigned, Unsigned) [resize] return Synth_Compare_Uns_Uns (Id_Ule); + when Iir_Predefined_Ieee_Numeric_Std_Le_Uns_Nat => + -- "<=" (Unsigned, Natural) + return Synth_Compare_Uns_Nat (Id_Ule); when Iir_Predefined_Ieee_Numeric_Std_Gt_Uns_Nat => -- ">" (Unsigned, Natural) @@ -528,6 +531,9 @@ package body Synth.Oper is | Iir_Predefined_Ieee_Std_Logic_Unsigned_Ge_Slv_Slv => -- ">=" (Unsigned, Unsigned) [resize] return Synth_Compare_Uns_Uns (Id_Uge); + when Iir_Predefined_Ieee_Numeric_Std_Ge_Uns_Nat => + -- ">=" (Unsigned, Natural) + return Synth_Compare_Uns_Nat (Id_Uge); when Iir_Predefined_Array_Element_Concat => declare -- cgit v1.2.3