From cb0c13d82e6d8f12029ace572b8ae4e788dcfa9a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 18 Jun 2021 15:33:42 +0200 Subject: First step towards aggregates. --- pyGHDL/dom/Aggregates.py | 81 ++++++++++++++++++++++++++++++++++++ pyGHDL/dom/Expression.py | 55 +++++++++++++++++++++++- pyGHDL/dom/Symbol.py | 7 ++++ pyGHDL/dom/_Translate.py | 4 +- pyGHDL/dom/formatting/prettyprint.py | 4 +- testsuite/pyunit/SimpleEntity.vhdl | 8 ++++ 6 files changed, 155 insertions(+), 4 deletions(-) create mode 100644 pyGHDL/dom/Aggregates.py diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py new file mode 100644 index 000000000..5a77b7e37 --- /dev/null +++ b/pyGHDL/dom/Aggregates.py @@ -0,0 +1,81 @@ +# ============================================================================= +# ____ _ _ ____ _ _ +# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___ +# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \ +# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | | +# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_| +# |_| |___/ +# ============================================================================= +# Authors: +# Patrick Lehmann +# +# Package module: DOM: VHDL design units (e.g. context or package). +# +# License: +# ============================================================================ +# Copyright (C) 2019-2021 Tristan Gingold +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# SPDX-License-Identifier: GPL-2.0-or-later +# ============================================================================ + +""" +This module contains all DOM classes for VHDL's design units (:class:`context `, +:class:`architecture `, :class:`package `, +:class:`package body `, :class:`context ` and +:class:`configuration `. + + +""" +from pydecor import export + +from pyVHDLModel.VHDLModel import ( + SimpleAggregateElement as VHDLModel_SimpleAggregateElement, + IndexedAggregateElement as VHDLModel_IndexedAggregateElement, + RangedAggregateElement as VHDLModel_RangedAggregateElement, + NamedAggregateElement as VHDLModel_NamedAggregateElement, + OthersAggregateElement as VHDLModel_OthersAggregateElement, Expression +) + + +__all__ = [] + + + +@export +class SimpleAggregateElement(VHDLModel_SimpleAggregateElement): + def __init__(self, expression: Expression): + super().__init__() + self._expression = expression + + +@export +class IndexedAggregateElement(VHDLModel_IndexedAggregateElement): + pass + + +@export +class RangedAggregateElement(VHDLModel_RangedAggregateElement): + pass + + +@export +class NamedAggregateElement(VHDLModel_NamedAggregateElement): + pass + + +@export +class OthersAggregateElement(VHDLModel_OthersAggregateElement): + pass diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 80ef2823c..bfe2cd9dd 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -30,6 +30,14 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ +from typing import List + +from pyGHDL.dom.Aggregates import OthersAggregateElement, SimpleAggregateElement, RangedAggregateElement, IndexedAggregateElement, NamedAggregateElement +from pyGHDL.dom.Symbol import EnumerationLiteralSymbol +from pyGHDL.libghdl import utils + +from pyGHDL.dom.Common import DOMException +from pyGHDL.dom._Utils import GetIirKindOfNode from pyGHDL.libghdl.vhdl import nodes from pydecor import export @@ -66,7 +74,8 @@ from pyVHDLModel.VHDLModel import ( ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression, RotateRightExpression as VHDLModel_RotateRightExpression, RotateLeftExpression as VHDLModel_RotateLeftExpression, - Expression, + Aggregate as VHDLModel_Aggregate, + Expression, AggregateElement, ) __all__ = [] @@ -350,3 +359,47 @@ class RotateLeftExpression(VHDLModel_RotateLeftExpression, _ParseBinaryExpressio super().__init__() self._leftOperand = left self._rightOperand = right + + +@export +class Aggregate(VHDLModel_Aggregate): + def __init__(self, elements: List[AggregateElement]): + super().__init__() + self._elements = elements + + @classmethod + def parse(cls, node): + from pyGHDL.dom._Translate import GetExpressionFromNode + + choices = [] + + choicesChain = nodes.Get_Association_Choices_Chain(node) + for item in utils.chain_iter(choicesChain): + kind = GetIirKindOfNode(item) + if kind == nodes.Iir_Kind.Choice_By_None: + value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) + choices.append(SimpleAggregateElement(value)) + elif kind == nodes.Iir_Kind.Choice_By_Expression: + index = GetExpressionFromNode(nodes.Get_Choice_Expression(item)) + value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) + choices.append(IndexedAggregateElement(index, value)) + elif kind == nodes.Iir_Kind.Choice_By_Range: + r = GetExpressionFromNode(nodes.Get_Choice_Range(item)) + value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) + choices.append(RangedAggregateElement(r, value)) + elif kind == nodes.Iir_Kind.Choice_By_Name: + name = EnumerationLiteralSymbol(nodes.Get_Choice_Name(item)) + value = GetExpressionFromNode(nodes.Get_Associated_Expr(item)) + choices.append(NamedAggregateElement(name, value)) + elif kind == nodes.Iir_Kind.Choice_By_Others: + expression = None + choices.append(OthersAggregateElement(expression)) + else: + raise DOMException( + "Unknown choice kind '{kindName}'({kind}) in aggregate '{aggr}'.".format( + kind=kind, kindName=kind.name, aggr=node + ) + ) + + return choices + diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index c7b681595..e722d2c0a 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -38,6 +38,7 @@ from pyGHDL.dom._Utils import NodeToName from pyVHDLModel.VHDLModel import ( SimpleSubTypeSymbol as VHDLModel_SimpleSubTypeSymbol, ConstrainedSubTypeSymbol as VHDLModel_ConstrainedSubTypeSymbol, + EnumerationLiteralSymbol as VHDLModel_EnumerationLiteralSymbol, SimpleObjectSymbol as VHDLModel_SimpleObjectSymbol, Constraint, ) @@ -45,6 +46,12 @@ from pyVHDLModel.VHDLModel import ( __all__ = [] +@export +class EnumerationLiteralSymbol(VHDLModel_EnumerationLiteralSymbol): + def __init__(self, literalName: str): + super().__init__(symbolName=literalName) + + @export class SimpleSubTypeSymbol(VHDLModel_SimpleSubTypeSymbol): def __init__(self, subTypeName: str): diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 9eb4937ec..f0ffe1cf1 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -53,7 +53,7 @@ from pyGHDL.dom.Expression import ( MultiplyExpression, DivisionExpression, InverseExpression, - ExponentiationExpression, + ExponentiationExpression, Aggregate, ) __all__ = [] @@ -135,7 +135,7 @@ __EXPRESSION_TRANSLATION = { nodes.Iir_Kind.Multiplication_Operator: MultiplyExpression, nodes.Iir_Kind.Division_Operator: DivisionExpression, nodes.Iir_Kind.Exponentiation_Operator: ExponentiationExpression, - # nodes.Iir_Kind.Aggregate: Aggregate + nodes.Iir_Kind.Aggregate: Aggregate, } diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 59fdd485b..1f71c87d5 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -45,7 +45,7 @@ from pyGHDL.dom.Expression import ( InverseExpression, AbsoluteExpression, NegationExpression, - ExponentiationExpression, + ExponentiationExpression, Aggregate, ) StringBuffer = List[str] @@ -375,5 +375,7 @@ class PrettyPrint: right=self.formatExpression(expression.RightOperand), operator=operator, ) + elif isinstance(expression, Aggregate): + print(Aggregate.Elements[0]) else: raise PrettyPrintException("Unhandled expression kind.") diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl index 9997c8d6d..8d5b034bb 100644 --- a/testsuite/pyunit/SimpleEntity.vhdl +++ b/testsuite/pyunit/SimpleEntity.vhdl @@ -27,3 +27,11 @@ begin end if; end process; end architecture behav; + +package package_1 is + constant ghdl : float := (3, 5); -- 2.3; +end package; + +package body package_1 is + constant ghdl : float := (1); -- => 2, 4 => 5, others => 10); -- .5; +end package body; -- cgit v1.2.3