From c9c04ce167a18eb0bf54dbef71244c892e8c04ec Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 21 Apr 2021 20:38:38 +0200
Subject: synth-vhdl_oper.adb: adjust previous patch and test

resize with two signed parameters extract the size of the second parameter
to resize the first one.
---
 src/synth/synth-vhdl_oper.adb          | 13 ++++++++++++-
 testsuite/synth/issue1731/testsuite.sh |  6 +++++-
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb
index f741d7fc7..26a886edf 100644
--- a/src/synth/synth-vhdl_oper.adb
+++ b/src/synth/synth-vhdl_oper.adb
@@ -1961,7 +1961,6 @@ package body Synth.Vhdl_Oper is
                   Create_Vec_Type_By_Length (W, Logic_Type));
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat
-            | Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sxt =>
@@ -1978,6 +1977,18 @@ package body Synth.Vhdl_Oper is
                                   W, Get_Location (Expr)),
                   Create_Vec_Type_By_Length (W, Logic_Type));
             end;
+         when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn =>
+            declare
+               B : Bound_Type;
+               W : Width;
+            begin
+               B := Get_Array_Bound (R.Typ, 1);
+               W := B.Len;
+               return Create_Value_Net
+                 (Build2_Sresize (Ctxt, Get_Net (Ctxt, L),
+                                  W, Get_Location (Expr)),
+                  Create_Vec_Type_By_Length (W, Logic_Type));
+            end;
          when Iir_Predefined_Ieee_Numeric_Std_Shf_Left_Uns_Nat
             | Iir_Predefined_Ieee_Numeric_Std_Shf_Left_Sgn_Nat
             | Iir_Predefined_Ieee_Std_Logic_Arith_Shl_Uns
diff --git a/testsuite/synth/issue1731/testsuite.sh b/testsuite/synth/issue1731/testsuite.sh
index 64ab16b12..557967b15 100755
--- a/testsuite/synth/issue1731/testsuite.sh
+++ b/testsuite/synth/issue1731/testsuite.sh
@@ -2,6 +2,10 @@
 
 . ../../testenv.sh
 
-synth_failure --std=08 -gfifo_depth=3 fifo.vhdl axis_conv1d9x1.vhdl -e
+GHDL_STD_FLAGS=--std=08
+synth -gfifo_depth=3 fifo.vhdl axis_conv1d9x1.vhdl -e > syn_axi_conv1d9x1.vhdl
+
+analyze syn_axi_conv1d9x1.vhdl
+clean
 
 echo "Test successful"
-- 
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