From c6e5cfd09db4bb1c6d1d8de21ccff5007c7f452d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 23 Feb 2020 08:45:26 +0100
Subject: testsuites/synth: add missing files.

---
 testsuite/synth/mem01/tb_sram02.vhdl | 47 +++++++++++++++++++++++++++++++++
 testsuite/synth/mem01/tb_sram03.vhdl | 50 ++++++++++++++++++++++++++++++++++++
 2 files changed, 97 insertions(+)
 create mode 100644 testsuite/synth/mem01/tb_sram02.vhdl
 create mode 100644 testsuite/synth/mem01/tb_sram03.vhdl

diff --git a/testsuite/synth/mem01/tb_sram02.vhdl b/testsuite/synth/mem01/tb_sram02.vhdl
new file mode 100644
index 000000000..2862f7400
--- /dev/null
+++ b/testsuite/synth/mem01/tb_sram02.vhdl
@@ -0,0 +1,47 @@
+entity tb_sram02 is
+end tb_sram02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sram02 is
+  signal addr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal wen : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.sram02
+    port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat,
+              wen_i => wen);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    addr <= "0000";
+    wdat <= x"02";
+    wen <= '1';
+    pulse;
+    assert rdat = x"02" severity failure;
+
+    addr <= "0100";
+    wdat <= x"03";
+    wait for 1 ns;
+    assert rdat = x"02" severity failure;
+    pulse;
+    assert rdat = x"03" severity failure;
+
+    addr <= "0000";
+    wen <= '0';
+    pulse;
+    assert rdat = x"02" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/tb_sram03.vhdl b/testsuite/synth/mem01/tb_sram03.vhdl
new file mode 100644
index 000000000..96cc80975
--- /dev/null
+++ b/testsuite/synth/mem01/tb_sram03.vhdl
@@ -0,0 +1,50 @@
+entity tb_sram03 is
+end tb_sram03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sram03 is
+  signal addr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal wen : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.sram03
+    port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat,
+              wen_i => wen);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    addr <= "0000";
+    wdat <= x"03";
+    wen <= '1';
+    pulse;
+
+    wdat <= x"41";
+    pulse;
+    assert rdat = x"03" severity failure;
+
+    addr <= "0100";
+    wdat <= x"07";
+    wait for 1 ns;
+    pulse;
+    pulse;
+    assert rdat = x"07" severity failure;
+
+    addr <= "0000";
+    wen <= '0';
+    pulse;
+    assert rdat = x"41" severity failure;
+
+    wait;
+  end process;
+end behav;
-- 
cgit v1.2.3