From c4f2d8305e6798a530f772887dee3592e872ac53 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 4 Jul 2022 21:11:56 +0200 Subject: netlists-disp_verilog: handle Id_Abs. Fix #2113 --- src/synth/netlists-disp_verilog.adb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index cd13a6d77..7d1354403 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -854,7 +854,7 @@ package body Netlists.Disp_Verilog is when Id_Neg => Disp_Template (" assign \o0 = -\i0;" & NL, Inst); when Id_Abs=> - Disp_Template (" \o0 <= std_logic_vector(abs \si0);" & NL, Inst); + Disp_Template (" \o0 <= \si0 >= 0 ? \i0 : -\i0;" & NL, Inst); when Id_Extract => Disp_Template (" assign \o0 = ", Inst); Disp_Extract (Inst); -- cgit v1.2.3