From bfa324688efd40f33b8473140f99af5f7fe5795c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 29 Mar 2023 20:44:08 +0200
Subject: testsuite/gna: add a test for #2356

---
 testsuite/gna/issue2356/repro1.vhdl   | 23 +++++++++++++++++++++++
 testsuite/gna/issue2356/repro_tb.vhdl | 29 +++++++++++++++++++++++++++++
 testsuite/gna/issue2356/testsuite.sh  | 11 +++++++++++
 3 files changed, 63 insertions(+)
 create mode 100644 testsuite/gna/issue2356/repro1.vhdl
 create mode 100644 testsuite/gna/issue2356/repro_tb.vhdl
 create mode 100755 testsuite/gna/issue2356/testsuite.sh

diff --git a/testsuite/gna/issue2356/repro1.vhdl b/testsuite/gna/issue2356/repro1.vhdl
new file mode 100644
index 000000000..8819b390f
--- /dev/null
+++ b/testsuite/gna/issue2356/repro1.vhdl
@@ -0,0 +1,23 @@
+entity repro1 is
+end;
+
+architecture sim of repro1 is
+    type SLV_vector is array (natural range <>) of bit_vector;
+
+    constant TEST_VAL_A : SLV_vector(3 downto 1)(7 downto 0) := (x"AD", x"12", x"DC");
+
+    -- Broken
+    constant TEST_SLICE : SLV_vector(1 downto 0) := TEST_VAL_A(3 downto 2);
+
+    -- Works
+    --constant TEST_SLICE : SLV_vector(1 downto 0)(TEST_VAL_A'element'range) := TEST_VAL_A(3 downto 2);
+
+begin
+    test_runner : process
+    begin
+        assert TEST_SLICE'high = 1 report "High should be 1" severity failure;
+        assert TEST_SLICE'low = 0 report "Low should be 0" severity failure;
+        wait;
+    end process test_runner;
+
+end architecture sim;
diff --git a/testsuite/gna/issue2356/repro_tb.vhdl b/testsuite/gna/issue2356/repro_tb.vhdl
new file mode 100644
index 000000000..233b25378
--- /dev/null
+++ b/testsuite/gna/issue2356/repro_tb.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.env.finish;
+
+entity repro_tb is
+end entity repro_tb;
+
+architecture sim of repro_tb is
+    type SLV_vector is array (natural range <>) of std_logic_vector;
+
+    constant TEST_VAL_A : SLV_vector(3 downto 1)(7 downto 0) := (x"AD", x"12", x"DC");
+
+    -- Broken
+    constant TEST_SLICE : SLV_vector(1 downto 0) := TEST_VAL_A(3 downto 2);
+
+    -- Works
+    --constant TEST_SLICE : SLV_vector(1 downto 0)(TEST_VAL_A'element'range) := TEST_VAL_A(3 downto 2);
+
+begin
+    test_runner : process
+    begin
+        assert TEST_SLICE'high = 1 report "High should be 1" severity failure;
+        assert TEST_SLICE'low = 0 report "Low should be 0" severity failure;
+        finish;
+    end process test_runner;
+
+end architecture sim;
diff --git a/testsuite/gna/issue2356/testsuite.sh b/testsuite/gna/issue2356/testsuite.sh
new file mode 100755
index 000000000..357ca3c67
--- /dev/null
+++ b/testsuite/gna/issue2356/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro_tb.vhdl
+elab_simulate repro_tb
+
+clean
+
+echo "Test successful"
-- 
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