From be7f5722c79f15796326be6842339dca2d797539 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 11 Sep 2022 08:01:19 +0200 Subject: simul: move assertions (not to trigger in case of errors) --- src/simul/simul-vhdl_simul.adb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index ed029cdf5..344302aa3 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -3051,9 +3051,6 @@ package body Simul.Vhdl_Simul is Status := Grt.Main.Run_Through_Longjump (Grt.Processes.Simulation_Init'Access); - pragma Assert (Areapools.Is_Empty (Expr_Pool)); - pragma Assert (Areapools.Is_Empty (Process_Pool)); - if Status = 0 then if Grt.Processes.Flag_AMS then Grt.Analog_Solver.Start; @@ -3062,6 +3059,9 @@ package body Simul.Vhdl_Simul is Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout); Assertion_Report_Handler := Assertion_Report_Msg'Access; + pragma Assert (Areapools.Is_Empty (Expr_Pool)); + pragma Assert (Areapools.Is_Empty (Process_Pool)); + loop if Break_Time < Grt.Processes.Next_Time then Grt.Processes.Next_Time := Break_Time; -- cgit v1.2.3