From bd29c849be41a8d15a6f6231a7664e8a7841a1b2 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 16 Aug 2019 12:13:54 +0200 Subject: synth: handle integers for displaying vhdl ports. --- src/synth/synth-disp_vhdl.adb | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 2abd0da44..351febe8b 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -143,6 +143,16 @@ package body Synth.Disp_Vhdl is New_Line; Idx := Idx + 1; end if; + when Iir_Kind_Integer_Type_Definition => + -- FIXME: signed or unsigned ? + Put (" " & Pfx & " <= to_integer (unsigned"); + if Desc.W = 1 then + Put ("'(0 => wrap_" & Pfx & ')'); + else + Put (" (wrap_" & Pfx & ')'); + end if; + Put_Line (");"); + Idx := Idx + 1; when Iir_Kind_Array_Type_Definition => if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type then -- Nothing to do. -- cgit v1.2.3