From bae9b806b461ce9a2231b683a4ff8b4ed487359b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 1 Jul 2016 06:21:31 +0200
Subject: Add testcase for issue #106

---
 testsuite/gna/issue106/ent.vhdl     | 16 ++++++++++++++++
 testsuite/gna/issue106/ent1.vhdl    | 16 ++++++++++++++++
 testsuite/gna/issue106/ent2.vhdl    | 20 ++++++++++++++++++++
 testsuite/gna/issue106/ent3.vhdl    | 14 ++++++++++++++
 testsuite/gna/issue106/testsuite.sh | 17 +++++++++++++++++
 5 files changed, 83 insertions(+)
 create mode 100644 testsuite/gna/issue106/ent.vhdl
 create mode 100644 testsuite/gna/issue106/ent1.vhdl
 create mode 100644 testsuite/gna/issue106/ent2.vhdl
 create mode 100644 testsuite/gna/issue106/ent3.vhdl
 create mode 100755 testsuite/gna/issue106/testsuite.sh

diff --git a/testsuite/gna/issue106/ent.vhdl b/testsuite/gna/issue106/ent.vhdl
new file mode 100644
index 000000000..b99496b7c
--- /dev/null
+++ b/testsuite/gna/issue106/ent.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+end entity ent;
+
+architecture arch of ent is
+  signal test: natural;
+begin
+  LL: if test=10 generate
+  elsif test=5 generate
+  end generate;
+end architecture arch;
+
+
diff --git a/testsuite/gna/issue106/ent1.vhdl b/testsuite/gna/issue106/ent1.vhdl
new file mode 100644
index 000000000..e1d3e7392
--- /dev/null
+++ b/testsuite/gna/issue106/ent1.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+end entity ent;
+
+architecture arch of ent is
+  constant test: natural := 2;
+begin
+  LL: if test=10 generate
+  elsif test=5 generate
+  end generate;
+end architecture arch;
+
+
diff --git a/testsuite/gna/issue106/ent2.vhdl b/testsuite/gna/issue106/ent2.vhdl
new file mode 100644
index 000000000..99b693fda
--- /dev/null
+++ b/testsuite/gna/issue106/ent2.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+end entity ent;
+
+architecture arch of ent is
+  constant test: natural := 3;
+begin
+  LL: if test=10 generate
+   begin
+   end;
+  elsif test=5 generate
+   begin
+   end;
+  end generate;
+end architecture arch;
+
+
diff --git a/testsuite/gna/issue106/ent3.vhdl b/testsuite/gna/issue106/ent3.vhdl
new file mode 100644
index 000000000..254960eb4
--- /dev/null
+++ b/testsuite/gna/issue106/ent3.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+end entity ent;
+
+architecture arch of ent is
+  signal test: natural;
+begin
+  LL: case test generate
+    when =>
+  end generate;
+end architecture arch;
diff --git a/testsuite/gna/issue106/testsuite.sh b/testsuite/gna/issue106/testsuite.sh
new file mode 100755
index 000000000..011b30fc0
--- /dev/null
+++ b/testsuite/gna/issue106/testsuite.sh
@@ -0,0 +1,17 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+analyze_failure ent.vhdl
+
+analyze ent1.vhdl
+elab_simulate ent
+
+analyze ent2.vhdl
+elab_simulate ent
+
+clean
+
+echo "Test successful"
-- 
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