From a785e3f228a5370d2f6550d893213a501a368cd0 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 31 May 2020 07:39:21 +0200 Subject: testsuite/synth/issue1069: renaming. --- testsuite/synth/issue1069/ram3.vhdl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/testsuite/synth/issue1069/ram3.vhdl b/testsuite/synth/issue1069/ram3.vhdl index f63c11ae0..67f155bd3 100644 --- a/testsuite/synth/issue1069/ram3.vhdl +++ b/testsuite/synth/issue1069/ram3.vhdl @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; -entity tdp_ram is +entity ram3 is generic ( ADDRWIDTH : positive := 12; WIDTH : positive := 8 @@ -22,9 +22,9 @@ entity tdp_ram is data_read_b : out std_logic_vector(WIDTH - 1 downto 0); data_write_b : in std_logic_vector(WIDTH - 1 downto 0) ); -end tdp_ram; +end ram3; -architecture behavioral of tdp_ram is +architecture behavioral of ram3 is signal reg_a : std_logic_vector(WIDTH - 1 downto 0); signal reg_b : std_logic_vector(WIDTH - 1 downto 0); begin -- cgit v1.2.3