From a6a956c6b35108ab171d67b54056ed14984590e2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 13 Jan 2021 18:51:32 +0100
Subject: testsuite/synth: add testcase for #1591

---
 testsuite/synth/issue1591/issue.vhdl   | 70 ++++++++++++++++++++++++++++++++++
 testsuite/synth/issue1591/repro1.vhdl  | 18 +++++++++
 testsuite/synth/issue1591/repro2.vhdl  | 20 ++++++++++
 testsuite/synth/issue1591/repro3.vhdl  | 16 ++++++++
 testsuite/synth/issue1591/repro4.vhdl  | 12 ++++++
 testsuite/synth/issue1591/testsuite.sh | 13 +++++++
 6 files changed, 149 insertions(+)
 create mode 100644 testsuite/synth/issue1591/issue.vhdl
 create mode 100644 testsuite/synth/issue1591/repro1.vhdl
 create mode 100644 testsuite/synth/issue1591/repro2.vhdl
 create mode 100644 testsuite/synth/issue1591/repro3.vhdl
 create mode 100644 testsuite/synth/issue1591/repro4.vhdl
 create mode 100755 testsuite/synth/issue1591/testsuite.sh

diff --git a/testsuite/synth/issue1591/issue.vhdl b/testsuite/synth/issue1591/issue.vhdl
new file mode 100644
index 000000000..242c1ee3b
--- /dev/null
+++ b/testsuite/synth/issue1591/issue.vhdl
@@ -0,0 +1,70 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+entity issue is
+  port (
+    clk : in std_logic
+  );
+end entity issue;
+
+
+architecture psl of issue is
+
+  signal a : boolean := true;
+
+begin
+
+
+  testG : if true generate
+
+    signal b : boolean := true;
+    signal c : boolean := false;
+
+  begin
+
+    c <= true;
+
+    -- All is sensitive to rising edge of clk
+    default clock is rising_edge(clk);
+
+    -- This assertion works
+    INITIAL_0_a : assert always a;
+
+    -- This assertion generates an ghdl-yosys-plugin error
+    -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
+    INITIAL_1_a : assert always b;
+
+    -- This assertion works
+    INITIAL_2_a : assert always c;
+
+  end generate testG;
+
+  -- Same error occurs when using a block instead of a generate
+  -- statement
+  testB : block is
+
+    signal b : boolean := true;
+    signal c : boolean := false;
+
+  begin
+
+    c <= true;
+
+    -- All is sensitive to rising edge of clk
+    default clock is rising_edge(clk);
+
+    -- This assertion works
+    INITIAL_0_a : assert always a;
+
+    -- This assertion generates an ghdl-yosys-plugin error
+    -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
+    INITIAL_1_a : assert always b;
+
+    -- This assertion works
+    INITIAL_2_a : assert always c;
+
+  end block testB;
+
+
+end architecture psl;
diff --git a/testsuite/synth/issue1591/repro1.vhdl b/testsuite/synth/issue1591/repro1.vhdl
new file mode 100644
index 000000000..df894a1e6
--- /dev/null
+++ b/testsuite/synth/issue1591/repro1.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity repro1 is
+  port (clk : in std_logic);
+end entity repro1;
+
+architecture psl of repro1 is
+  signal b : boolean := true;
+begin
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion generates an ghdl-yosys-plugin error
+  -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
+  INITIAL_1_a : assert always b;
+end architecture psl;
+
diff --git a/testsuite/synth/issue1591/repro2.vhdl b/testsuite/synth/issue1591/repro2.vhdl
new file mode 100644
index 000000000..c0ef4f21a
--- /dev/null
+++ b/testsuite/synth/issue1591/repro2.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity repro1 is
+  port (clk : in std_logic);
+end entity repro1;
+
+architecture psl of repro1 is
+begin
+  testG : if true generate
+    signal b : boolean := true;
+  begin
+    -- All is sensitive to rising edge of clk
+    default clock is rising_edge(clk);
+
+    -- This assertion generates an ghdl-yosys-plugin error
+    -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
+    INITIAL_1_a : assert always b;
+  end generate testG;
+end architecture psl;
diff --git a/testsuite/synth/issue1591/repro3.vhdl b/testsuite/synth/issue1591/repro3.vhdl
new file mode 100644
index 000000000..cd176d557
--- /dev/null
+++ b/testsuite/synth/issue1591/repro3.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity repro3 is
+  port (clk : in std_logic;
+        o : out boolean);
+end entity repro3;
+
+architecture psl of repro3 is
+begin
+  testG : if true generate
+    signal b : boolean := true;
+  begin
+    assert b;
+  end generate testG;
+end architecture psl;
diff --git a/testsuite/synth/issue1591/repro4.vhdl b/testsuite/synth/issue1591/repro4.vhdl
new file mode 100644
index 000000000..44f06e651
--- /dev/null
+++ b/testsuite/synth/issue1591/repro4.vhdl
@@ -0,0 +1,12 @@
+entity repro4 is
+  port (o : out boolean);
+end entity repro4;
+
+architecture arch of repro4 is
+begin
+  testG : if true generate
+    signal b : boolean := true;
+  begin
+    o <= b;
+  end generate testG;
+end;
diff --git a/testsuite/synth/issue1591/testsuite.sh b/testsuite/synth/issue1591/testsuite.sh
new file mode 100755
index 000000000..3a8878508
--- /dev/null
+++ b/testsuite/synth/issue1591/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+synth_analyze issue
+synth_analyze repro1
+synth_analyze repro2
+synth_analyze repro3
+synth_analyze repro4
+
+clean
+echo "Test successful"
-- 
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