From a05d3cb7bd8eb037c3057c2ef8d066df1489ce2d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 26 Mar 2021 18:43:15 +0100
Subject: testsuite/synth: add a test for #1698

---
 testsuite/synth/issue1698/ent.psl      |  6 ++++++
 testsuite/synth/issue1698/ent.vhdl     | 28 ++++++++++++++++++++++++++++
 testsuite/synth/issue1698/testsuite.sh |  7 +++++++
 3 files changed, 41 insertions(+)
 create mode 100644 testsuite/synth/issue1698/ent.psl
 create mode 100644 testsuite/synth/issue1698/ent.vhdl
 create mode 100755 testsuite/synth/issue1698/testsuite.sh

diff --git a/testsuite/synth/issue1698/ent.psl b/testsuite/synth/issue1698/ent.psl
new file mode 100644
index 000000000..db646248f
--- /dev/null
+++ b/testsuite/synth/issue1698/ent.psl
@@ -0,0 +1,6 @@
+vunit i_ent(ent(rtl))
+{
+   default clock is rising_edge(clk);
+
+   assert always {[+]; input} |=> {output};
+}
diff --git a/testsuite/synth/issue1698/ent.vhdl b/testsuite/synth/issue1698/ent.vhdl
new file mode 100644
index 000000000..aa5759faf
--- /dev/null
+++ b/testsuite/synth/issue1698/ent.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+   port (
+      clk    : in  std_logic;
+      input  : in  std_logic;
+      output : out std_logic
+   );
+end entity ent;
+
+architecture rtl of ent is
+
+   signal r : std_logic;
+
+begin
+
+   process (clk)
+   begin
+      if rising_edge(clk) then
+         r <= input;
+      end if;
+   end process;
+
+   output <= r;
+
+end architecture rtl;
+
diff --git a/testsuite/synth/issue1698/testsuite.sh b/testsuite/synth/issue1698/testsuite.sh
new file mode 100755
index 000000000..2f64586ab
--- /dev/null
+++ b/testsuite/synth/issue1698/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --std=08 ent.vhdl ent.psl -e ent > syn_ent.vhdl
+
+echo "Test successful"
-- 
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