From 9e421ddc712d8c3346604ac36a0a83419ad9464c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 6 Aug 2021 03:04:16 +0200 Subject: testsuite/gna: add a test for #1723 --- testsuite/gna/issue1723/my_pkg.vhdl | 18 ++++++++++++++++++ testsuite/gna/issue1723/repro.vhdl | 17 +++++++++++++++++ testsuite/gna/issue1723/testsuite.sh | 13 +++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 testsuite/gna/issue1723/my_pkg.vhdl create mode 100644 testsuite/gna/issue1723/repro.vhdl create mode 100755 testsuite/gna/issue1723/testsuite.sh diff --git a/testsuite/gna/issue1723/my_pkg.vhdl b/testsuite/gna/issue1723/my_pkg.vhdl new file mode 100644 index 000000000..71b245d86 --- /dev/null +++ b/testsuite/gna/issue1723/my_pkg.vhdl @@ -0,0 +1,18 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package my_pkg is + + type my_vector is array (natural range <>) of integer; + type my_vector_vector is array (natural range <>) of my_vector; + + constant C_1 : my_vector(1 downto 0) := (others => 1); + constant C_2 : my_vector(2 downto 0) := (others => 2); + + constant C_FOO : my_vector_vector(1 downto 0) := ( + 0 => C_1, + 1 => C_2 + ); + +end package my_pkg; diff --git a/testsuite/gna/issue1723/repro.vhdl b/testsuite/gna/issue1723/repro.vhdl new file mode 100644 index 000000000..c64667efb --- /dev/null +++ b/testsuite/gna/issue1723/repro.vhdl @@ -0,0 +1,17 @@ +entity repro is +end; + +architecture behav of repro is + type my_vector is array (natural range <>) of integer; + type my_vector_vector is array (natural range <>) of my_vector; + + constant C_1 : my_vector(1 downto 0) := (others => 1); + constant C_2 : my_vector(2 downto 0) := (others => 2); + + constant C_FOO : my_vector_vector(1 downto 0) := ( + 0 => C_1, + 1 => C_2 + ); +begin +end; + diff --git a/testsuite/gna/issue1723/testsuite.sh b/testsuite/gna/issue1723/testsuite.sh new file mode 100755 index 000000000..1610fe253 --- /dev/null +++ b/testsuite/gna/issue1723/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze_failure -Werror repro.vhdl + +analyze repro.vhdl +elab_simulate_failure repro + +clean + +echo "Test successful" -- cgit v1.2.3