From 9b22045bb3e1646b3b7c6d866c11f5b2d556beab Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 22 Dec 2016 06:35:59 +0100
Subject: Add testcase for #242

---
 testsuite/gna/issue242/test.vhdl    | 18 ++++++++++++++++++
 testsuite/gna/issue242/testsuite.sh | 11 +++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 testsuite/gna/issue242/test.vhdl
 create mode 100755 testsuite/gna/issue242/testsuite.sh

diff --git a/testsuite/gna/issue242/test.vhdl b/testsuite/gna/issue242/test.vhdl
new file mode 100644
index 000000000..5598c388c
--- /dev/null
+++ b/testsuite/gna/issue242/test.vhdl
@@ -0,0 +1,18 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+
+ENTITY test IS
+END ENTITY test;
+
+ARCHITECTURE rtl OF test IS
+
+  TYPE test_data_t IS ARRAY (0 TO 2) OF natural;
+
+  TYPE test_vector_t IS ARRAY (0 TO 7) OF test_data_t;
+
+  CONSTANT C_TEST_VECTOR : test_vector_t := (OTHERS => test_data_t'(0, 0, 0));
+
+BEGIN
+
+END ARCHITECTURE rtl;
diff --git a/testsuite/gna/issue242/testsuite.sh b/testsuite/gna/issue242/testsuite.sh
new file mode 100755
index 000000000..1d84c0f57
--- /dev/null
+++ b/testsuite/gna/issue242/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"
-- 
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