From 95632804220716d4993d3e4b0d0cba06d984a837 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 10 Sep 2015 20:57:12 +0200 Subject: Add reproducer for ticket92. --- testsuite/gna/ticket92/cover_report.vhd | 59 +++++++++++++++++++++++++++++++++ testsuite/gna/ticket92/testsuite.sh | 11 ++++++ 2 files changed, 70 insertions(+) create mode 100644 testsuite/gna/ticket92/cover_report.vhd create mode 100755 testsuite/gna/ticket92/testsuite.sh diff --git a/testsuite/gna/ticket92/cover_report.vhd b/testsuite/gna/ticket92/cover_report.vhd new file mode 100644 index 000000000..e7f1e3054 --- /dev/null +++ b/testsuite/gna/ticket92/cover_report.vhd @@ -0,0 +1,59 @@ +library ieee; + use ieee.std_logic_1164.all; + +library std; + use std.env.all; + + + +entity cover_report is +end entity cover_report; + + + +architecture test of cover_report is + + + signal s_a : std_logic; + signal s_b : std_logic; + signal s_c : std_logic; + signal s_clk : std_logic := '0'; + + +begin + + + s_clk <= not(s_clk) after 5 ns; + + + process is + begin + s_a <= '0'; + s_b <= '0'; + s_c <= '0'; + wait until rising_edge(s_clk); + s_a <= '1'; + wait until rising_edge(s_clk); + s_a <= '0'; + s_b <= '1'; + wait until rising_edge(s_clk); + s_b <= '0'; + s_c <= '1'; + wait until rising_edge(s_clk); + s_c <= '0'; + stop(0); + end process; + + + -- psl default clock is rising_edge(s_clk); + -- + -- psl property test_p is ({s_a; s_b}); + -- + -- DOES WORK + -- -- psl TEST : cover test_p; + -- + -- DOESN'T WORK: + -- psl cover test_p report "Covered"; + + +end architecture test; diff --git a/testsuite/gna/ticket92/testsuite.sh b/testsuite/gna/ticket92/testsuite.sh new file mode 100755 index 000000000..8a76a9833 --- /dev/null +++ b/testsuite/gna/ticket92/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS="--std=08 -fpsl" + +analyze cover_report.vhd +elab_simulate cover_report +clean + +echo "Test successful" -- cgit v1.2.3