From f276ac42e251190c4f6cb2bbc4b488923f328551 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 25 Dec 2022 13:42:40 +0100 Subject: Updated pretty printing. --- pyGHDL/dom/formatting/prettyprint.py | 45 ++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 0f548210b..26a964aec 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -133,37 +133,33 @@ class PrettyPrint: def formatLibrary(self, library: Library, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append(f"{prefix}Entities:") - for entity in library.Entities: - buffer.append(f"{prefix} - {entity.Identifier}({', '.join([a.Identifier for a in entity.Architectures])})") + buffer.append(f"{prefix}Contexts:") + for context in library.Contexts.values(): + buffer.append(f"{prefix} - {context.Identifier}") buffer.append(f"{prefix}Packages:") - for package in library.Packages: + for package in library.Packages.values(): if isinstance(package, Package): buffer.append(f"{prefix} - {package.Identifier}") elif isinstance(package, PackageInstantiation): buffer.append(f"{prefix} - {package.Identifier} instantiate from {package.PackageReference}") + buffer.append(f"{prefix}Entities:") + for entity in library.Entities.values(): + buffer.append(f"{prefix} - {entity.Identifier}({', '.join([a.Identifier for a in entity.Architectures])})") buffer.append(f"{prefix}Configurations:") - for configuration in library.Configurations: + for configuration in library.Configurations.values(): buffer.append(f"{prefix} - {configuration.Identifier}") - buffer.append(f"{prefix}Contexts:") - for context in library.Contexts: - buffer.append(f"{prefix} - {context.Identifier}") return buffer def formatDocument(self, document: Document, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append(f"{prefix}Entities:") - for entity in document.Entities: - for line in self.formatEntity(entity, level + 1): - buffer.append(line) - buffer.append(f"{prefix}Architectures:") - for architecture in document.Architectures: - for line in self.formatArchitecture(architecture, level + 1): + buffer.append(f"{prefix}Contexts:") + for context in document.Contexts.values(): + for line in self.formatContext(context, level + 1): buffer.append(line) buffer.append(f"{prefix}Packages:") - for package in document.Packages: + for package in document.Packages.values(): if isinstance(package, Package): gen = self.formatPackage else: @@ -172,17 +168,22 @@ class PrettyPrint: for line in gen(package, level + 1): buffer.append(line) buffer.append(f"{prefix}PackageBodies:") - for packageBodies in document.PackageBodies: + for packageBodies in document.PackageBodies.values(): for line in self.formatPackageBody(packageBodies, level + 1): buffer.append(line) + buffer.append(f"{prefix}Entities:") + for entity in document.Entities.values(): + for line in self.formatEntity(entity, level + 1): + buffer.append(line) + buffer.append(f"{prefix}Architectures:") + for architectures in document.Architectures.values(): + for architecture in architectures.values(): + for line in self.formatArchitecture(architecture, level + 1): + buffer.append(line) buffer.append(f"{prefix}Configurations:") - for configuration in document.Configurations: + for configuration in document.Configurations.values(): for line in self.formatConfiguration(configuration, level + 1): buffer.append(line) - buffer.append(f"{prefix}Contexts:") - for context in document.Contexts: - for line in self.formatContext(context, level + 1): - buffer.append(line) return buffer -- cgit v1.2.3 From 8e1b0568057bbe6d81d68aa47b9b6fc42bdb2de4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 25 Dec 2022 15:43:52 +0100 Subject: Added one-line code documentations. --- pyGHDL/dom/formatting/prettyprint.py | 28 ++++++++++++++++++---- .../dom/examples/StopWatch/StopWatch.pkg.vhdl | 2 +- .../dom/examples/StopWatch/Utilities.pkg.vhdl | 1 + .../dom/examples/StopWatch/seg7_Encoder.vhdl | 1 + .../dom/examples/StopWatch/toplevel.Encoder.vhdl | 1 + 5 files changed, 28 insertions(+), 5 deletions(-) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 26a964aec..7c99e1d87 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -114,6 +114,14 @@ class PrettyPrint: # def __init__(self): # self._buffer = [] + def CleanupDocumentationBlocks(self, documentationContent: str, level: int = 0): + prefix = " " * level + if documentationContent is None: + return prefix + + documentationLines = documentationContent.split("\n") + return f"{prefix}{documentationLines[0][2:].lstrip()}" + def formatDesign(self, design: Design, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level @@ -190,10 +198,12 @@ class PrettyPrint: def formatEntity(self, entity: Entity, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level + documentationFirstLine = self.CleanupDocumentationBlocks(entity.Documentation) buffer.append( f"{prefix}- Name: {entity.Identifier}\n" f"{prefix} File: {entity.Position.Filename.name}\n" - f"{prefix} Position: {entity.Position.Line}:{entity.Position.Column}" + f"{prefix} Position: {entity.Position.Line}:{entity.Position.Column}\n" + f"{prefix} Documentation: {documentationFirstLine}" ) buffer.append(f"{prefix} Generics:") for generic in entity.GenericItems: @@ -219,10 +229,12 @@ class PrettyPrint: def formatArchitecture(self, architecture: Architecture, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level + documentationFirstLine = self.CleanupDocumentationBlocks(architecture.Documentation) buffer.append( f"{prefix}- Name: {architecture.Identifier}\n" f"{prefix} File: {architecture.Position.Filename.name}\n" - f"{prefix} Position: {architecture.Position.Line}:{architecture.Position.Column}" + f"{prefix} Position: {architecture.Position.Line}:{architecture.Position.Column}\n" + f"{prefix} Documentation: {documentationFirstLine}" ) buffer.append(f"{prefix} Entity: {architecture.Entity.SymbolName}") buffer.append(f"{prefix} Declared:") @@ -244,6 +256,7 @@ class PrettyPrint: def formatComponent(self, component: Component, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level + documentationFirstLine = self.CleanupDocumentationBlocks(component.Documentation) buffer.append(f"{prefix}- Component: {component.Identifier}") buffer.append(f"{prefix} Generics:") for generic in component.GenericItems: @@ -259,10 +272,12 @@ class PrettyPrint: def formatPackage(self, package: Package, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level + documentationFirstLine = self.CleanupDocumentationBlocks(package.Documentation) buffer.append( f"{prefix}- Name: {package.Identifier}\n" f"{prefix} File: {package.Position.Filename.name}\n" - f"{prefix} Position: {package.Position.Line}:{package.Position.Column}" + f"{prefix} Position: {package.Position.Line}:{package.Position.Column}\n" + f"{prefix} Documentation: {documentationFirstLine}" ) buffer.append(f"{prefix} Declared:") for item in package.DeclaredItems: @@ -274,6 +289,7 @@ class PrettyPrint: def formatPackageInstance(self, package: PackageInstantiation, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level + documentationFirstLine = self.CleanupDocumentationBlocks(package.Documentation) buffer.append(f"{prefix}- Name: {package.Identifier}") buffer.append(f"{prefix} Package: {package.PackageReference!s}") buffer.append(f"{prefix} Generic Map: ...") @@ -286,7 +302,11 @@ class PrettyPrint: def formatPackageBody(self, packageBody: PackageBody, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append(f"{prefix}- Name: {packageBody.Identifier}") + documentationFirstLine = self.CleanupDocumentationBlocks(packageBody.Documentation) + buffer.append( + f"{prefix}- Name: {packageBody.Identifier}\n" + f"{prefix} Documentation: {documentationFirstLine}" + ) buffer.append(f"{prefix} Declared:") for item in packageBody.DeclaredItems: for line in self.formatDeclaredItems(item, level + 1): diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl index 3bcafdd6d..1a40718aa 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl @@ -7,7 +7,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; - +-- Package with stop watch specific types. package StopWatch_pkg is subtype T_BCD is unsigned(3 downto 0); type T_BCD_Vector is array(natural range <>) of T_BCD; diff --git a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl index 8daf39614..16a40ccba 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl @@ -8,6 +8,7 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; +-- Useful utility functions and types. package Utilities is type freq is range integer'low to integer'high units Hz; diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl index e4c731ff9..3742982be 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl @@ -11,6 +11,7 @@ use work.Utilities.all; use work.StopWatch_pkg.all; +-- Encoder that translates from 4-bit binary (BCD) to 7-segment code. entity seg7_Encoder is port ( BCDValue : in T_BCD; diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl index 7775a6eb6..58294b67f 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl @@ -11,6 +11,7 @@ use work.Utilities.all; use work.StopWatch_pkg.all; +-- Toplevel module to demonstrate the translation of 4 slide-switches to 1 digit 7-segment display. entity toplevel is port ( NexysA7_GPIO_Switch : in std_logic_vector(3 downto 0); -- cgit v1.2.3 From c02d6c4372f2250321cdaed0105cdc5273370bbc Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 25 Dec 2022 20:06:20 +0100 Subject: Removed declarations of __all__ when not needed by export. --- pyGHDL/dom/Aggregates.py | 2 -- pyGHDL/dom/DesignUnit.py | 3 --- pyGHDL/dom/Expression.py | 3 --- pyGHDL/dom/InterfaceItem.py | 3 --- pyGHDL/dom/Literal.py | 2 -- pyGHDL/dom/Misc.py | 2 -- pyGHDL/dom/Names.py | 2 -- pyGHDL/dom/NonStandard.py | 2 -- pyGHDL/dom/Object.py | 2 -- pyGHDL/dom/PSL.py | 3 --- pyGHDL/dom/Range.py | 2 -- pyGHDL/dom/_Translate.py | 3 --- pyGHDL/dom/_Utils.py | 2 -- 13 files changed, 31 deletions(-) diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py index 02e071cb5..a1fe40866 100644 --- a/pyGHDL/dom/Aggregates.py +++ b/pyGHDL/dom/Aggregates.py @@ -54,8 +54,6 @@ from pyGHDL.libghdl._types import Iir from pyGHDL.dom import DOMMixin from pyGHDL.dom.Range import Range -__all__ = [] - @export class SimpleAggregateElement(VHDLModel_SimpleAggregateElement, DOMMixin): diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index eebf888bc..eb7dfcb88 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -82,9 +82,6 @@ from pyGHDL.dom.Names import SimpleName from pyGHDL.dom.Symbol import EntitySymbol -__all__ = [] - - @export class LibraryClause(VHDLModel_LibraryClause, DOMMixin): def __init__(self, libraryNode: Iir, symbols: Iterable[Name]): diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 4a61597e2..81ecfa380 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -104,9 +104,6 @@ from pyGHDL.dom.Aggregates import ( ) -__all__ = [] - - class _ParseUnaryExpressionMixin: @classmethod def parse(cls, node: Iir) -> VHDLModel_UnaryExpression: diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py index aa63f3094..44b67a79c 100644 --- a/pyGHDL/dom/InterfaceItem.py +++ b/pyGHDL/dom/InterfaceItem.py @@ -57,9 +57,6 @@ from pyGHDL.dom._Utils import GetNameOfNode, GetModeOfNode, GetDocumentationOfNo from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode, GetExpressionFromNode -__all__ = [] - - @export class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, DOMMixin): def __init__( diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py index c054273c4..e8a87bc19 100644 --- a/pyGHDL/dom/Literal.py +++ b/pyGHDL/dom/Literal.py @@ -48,8 +48,6 @@ from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin from pyGHDL.dom._Utils import GetNameOfNode -__all__ = [] - @export class NullLiteral(VHDLModel_NullLiteral, DOMMixin): diff --git a/pyGHDL/dom/Misc.py b/pyGHDL/dom/Misc.py index 8f85db222..71860f676 100644 --- a/pyGHDL/dom/Misc.py +++ b/pyGHDL/dom/Misc.py @@ -44,8 +44,6 @@ from pyGHDL.libghdl._types import Iir from pyGHDL.dom import DOMMixin from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode -__all__ = [] - @export class Alias(VHDLModel_Alias, DOMMixin): diff --git a/pyGHDL/dom/Names.py b/pyGHDL/dom/Names.py index d601739db..c66d20661 100644 --- a/pyGHDL/dom/Names.py +++ b/pyGHDL/dom/Names.py @@ -48,8 +48,6 @@ from pyVHDLModel.SyntaxModel import ( from pyGHDL.libghdl._types import Iir from pyGHDL.dom import DOMMixin -__all__ = [] - @export class SimpleName(VHDLModel_SimpleName, DOMMixin): diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py index 0a2ead728..0bfc774bf 100644 --- a/pyGHDL/dom/NonStandard.py +++ b/pyGHDL/dom/NonStandard.py @@ -86,8 +86,6 @@ from pyGHDL.dom.DesignUnit import ( ) from pyGHDL.dom.PSL import VerificationUnit, VerificationProperty, VerificationMode -__all__ = [] - @export class Design(VHDLModel_Design): diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py index 1079eae4a..953fae02a 100644 --- a/pyGHDL/dom/Object.py +++ b/pyGHDL/dom/Object.py @@ -50,8 +50,6 @@ from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode -__all__ = [] - @export class Constant(VHDLModel_Constant, DOMMixin): diff --git a/pyGHDL/dom/PSL.py b/pyGHDL/dom/PSL.py index 0217e0639..f935f7849 100644 --- a/pyGHDL/dom/PSL.py +++ b/pyGHDL/dom/PSL.py @@ -53,9 +53,6 @@ from pyGHDL.dom import DOMMixin from pyGHDL.dom._Utils import GetNameOfNode -__all__ = [] - - @export class VerificationUnit(VHDLModel_VerificationUnit, DOMMixin): def __init__( diff --git a/pyGHDL/dom/Range.py b/pyGHDL/dom/Range.py index c6f783139..2674a43f4 100644 --- a/pyGHDL/dom/Range.py +++ b/pyGHDL/dom/Range.py @@ -34,8 +34,6 @@ from pyTooling.Decorators import export from pyVHDLModel.SyntaxModel import Range as VHDLModel_Range -__all__ = [] - @export class Range(VHDLModel_Range): diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 20d173710..f471824d3 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -173,9 +173,6 @@ from pyGHDL.dom.Misc import Alias from pyGHDL.dom.PSL import DefaultClock -__all__ = [] - - @export def GetNameFromNode(node: Iir) -> Name: kind = GetIirKindOfNode(node) diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 83f10eae8..8bc1f34a0 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -40,8 +40,6 @@ from pyGHDL.libghdl.vhdl import nodes, utils from pyGHDL.libghdl.vhdl.nodes import Null_Iir from pyGHDL.dom import DOMException -__all__ = [] - __MODE_TRANSLATION = { nodes.Iir_Mode.In_Mode: Mode.In, nodes.Iir_Mode.Out_Mode: Mode.Out, -- cgit v1.2.3 From 4be45cbc3b4fc20eae8f817fce7bd508d6964691 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 25 Dec 2022 22:27:02 +0100 Subject: Converted more symbols for packages and contexts. --- pyGHDL/dom/DesignUnit.py | 45 ++++++++++++++++++++++++++++++++++++--------- pyGHDL/dom/NonStandard.py | 8 ++++---- pyGHDL/dom/Symbol.py | 41 +++++++++++++++++++++++++++++++++++++++-- 3 files changed, 79 insertions(+), 15 deletions(-) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index eb7dfcb88..3e3784dde 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -39,7 +39,7 @@ This module contains all DOM classes for VHDL's design units (:class:`context Union[PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: + kind = GetIirKindOfNode(node) + prefixName = cls.GetPackageSymbol(nodes.Get_Prefix(node)) + if kind == nodes.Iir_Kind.Selected_Name: + name = GetNameOfNode(node) + return PackageMembersReferenceSymbol(node, name, prefixName) + elif kind == nodes.Iir_Kind.Selected_By_All_Name: + return AllPackageMembersReferenceSymbol(node, prefixName) + else: + raise DOMException() + + @classmethod + def GetPackageSymbol(cls, node: Iir) -> PackageReferenceSymbol: + kind = GetIirKindOfNode(node) + if kind == nodes.Iir_Kind.Selected_Name: + name = GetNameOfNode(node) + prefixName = cls.GetLibrarySymbol(nodes.Get_Prefix(node)) + return PackageReferenceSymbol(node, name, prefixName) + else: + raise DOMException() - uses = [PackageReferenceSymbol(GetNameFromNode(nodes.Get_Selected_Name(useNode)))] + @classmethod + def GetLibrarySymbol(cls, node: Iir) -> LibraryReferenceSymbol: + kind = GetIirKindOfNode(node) + if kind == nodes.Iir_Kind.Simple_Name: + name = GetNameOfNode(node) + return LibraryReferenceSymbol(node, name) + else: + raise DOMException() + + @classmethod + def parse(cls, useNode: Iir): + uses = [cls.GetPackageMemberSymbol(nodes.Get_Selected_Name(useNode))] for use in utils.chain_iter(nodes.Get_Use_Clause_Chain(useNode)): - uses.append(PackageReferenceSymbol(GetNameFromNode(nodes.Get_Selected_Name(use)))) + uses.append(cls.GetPackageMemberSymbol(nodes.Get_Selected_Name(use))) return cls(useNode, uses) diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py index 0bfc774bf..64c34b527 100644 --- a/pyGHDL/dom/NonStandard.py +++ b/pyGHDL/dom/NonStandard.py @@ -48,7 +48,6 @@ from pyVHDLModel.SyntaxModel import ( Design as VHDLModel_Design, Library as VHDLModel_Library, Document as VHDLModel_Document, - LibraryReferenceSymbol, ) from pyGHDL.libghdl import ( @@ -82,8 +81,8 @@ from pyGHDL.dom.DesignUnit import ( PackageInstantiation, LibraryClause, UseClause, - ContextReference, -) + ContextReference, ) +from pyGHDL.dom.Symbol import LibraryReferenceSymbol from pyGHDL.dom.PSL import VerificationUnit, VerificationProperty, VerificationMode @@ -195,7 +194,8 @@ class Document(VHDLModel_Document): for item in utils.chain_iter(context): itemKind = GetIirKindOfNode(item) if itemKind is nodes.Iir_Kind.Library_Clause: - contextNames.append(LibraryReferenceSymbol(SimpleName(item, GetNameOfNode(item)))) + libraryIdentifier = GetNameOfNode(item) + contextNames.append(LibraryReferenceSymbol(item, libraryIdentifier)) if nodes.Get_Has_Identifier_List(item): continue diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 0dd0fefa9..ed1acb7b1 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -34,7 +34,6 @@ from typing import List, Iterator from pyTooling.Decorators import export, InheritDocString -from pyGHDL.dom.Names import SimpleName from pyVHDLModel.SyntaxModel import ( EntitySymbol as VHDLModel_EntitySymbol, ArchitectureSymbol as VHDLModel_ArchitectureSymbol, @@ -46,13 +45,51 @@ from pyVHDLModel.SyntaxModel import ( IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol, ConstraintUnion, Name, + LibraryReferenceSymbol as VHDLModel_LibraryReferenceSymbol, + PackageReferenceSymbol as VHDLModel_PackageReferenceSymbol, + PackageMembersReferenceSymbol as VHDLModel_PackageMembersReferenceSymbol, + AllPackageMembersReferenceSymbol as VHDLModel_AllPackageMembersReferenceSymbol, + ContextReferenceSymbol as VHDLModel_ContextReferenceSymbol, ) from pyGHDL.libghdl._types import Iir from pyGHDL.dom import DOMMixin +from pyGHDL.dom.Names import SimpleName from pyGHDL.dom.Range import Range -__all__ = [] +@export +class LibraryReferenceSymbol(VHDLModel_LibraryReferenceSymbol, DOMMixin): + def __init__(self, libraryNode: Iir, identifier: str): + super().__init__(identifier) + DOMMixin.__init__(self, libraryNode) + + +@export +class PackageReferenceSymbol(VHDLModel_PackageReferenceSymbol, DOMMixin): + def __init__(self, libraryNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): + super().__init__(identifier, prefix) + DOMMixin.__init__(self, libraryNode) + + +@export +class PackageMembersReferenceSymbol(VHDLModel_PackageMembersReferenceSymbol, DOMMixin): + def __init__(self, libraryNode: Iir, identifier: str, prefix: PackageReferenceSymbol): + super().__init__(identifier, prefix) + DOMMixin.__init__(self, libraryNode) + + +@export +class AllPackageMembersReferenceSymbol(VHDLModel_AllPackageMembersReferenceSymbol, DOMMixin): + def __init__(self, libraryNode: Iir, prefix: PackageReferenceSymbol): + super().__init__(prefix) + DOMMixin.__init__(self, libraryNode) + + +@export +class ContextReferenceSymbol(VHDLModel_ContextReferenceSymbol, DOMMixin): + def __init__(self, libraryNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): + super().__init__(identifier, prefix) + DOMMixin.__init__(self, libraryNode) @export -- cgit v1.2.3 From 283418269b3f5e351415dc6e8946437a1781941c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 26 Dec 2022 09:14:46 +0100 Subject: New handling of symbols. --- pyGHDL/dom/DesignUnit.py | 49 +++++----------------- pyGHDL/dom/_Utils.py | 31 ++++++++++++++ .../dom/examples/StopWatch/StopWatch.ctx.vhdl | 21 ++++++++++ .../dom/examples/StopWatch/Utilities.ctx.vhdl | 12 ++++++ 4 files changed, 74 insertions(+), 39 deletions(-) create mode 100644 testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl create mode 100644 testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 3e3784dde..8ccdb91bb 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -69,7 +69,7 @@ from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, Position, DOMException -from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetIirKindOfNode +from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol from pyGHDL.dom._Translate import ( GetGenericsFromChainedNodes, GetPortsFromChainedNodes, @@ -77,7 +77,7 @@ from pyGHDL.dom._Translate import ( GetConcurrentStatementsFromChainedNodes, ) from pyGHDL.dom.Names import SimpleName -from pyGHDL.dom.Symbol import EntitySymbol, LibraryReferenceSymbol, PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol, ContextReferenceSymbol +from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol @export @@ -93,42 +93,11 @@ class UseClause(VHDLModel_UseClause, DOMMixin): super().__init__(symbols) DOMMixin.__init__(self, useNode) - @classmethod - def GetPackageMemberSymbol(cls, node: Iir) -> Union[PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: - kind = GetIirKindOfNode(node) - prefixName = cls.GetPackageSymbol(nodes.Get_Prefix(node)) - if kind == nodes.Iir_Kind.Selected_Name: - name = GetNameOfNode(node) - return PackageMembersReferenceSymbol(node, name, prefixName) - elif kind == nodes.Iir_Kind.Selected_By_All_Name: - return AllPackageMembersReferenceSymbol(node, prefixName) - else: - raise DOMException() - - @classmethod - def GetPackageSymbol(cls, node: Iir) -> PackageReferenceSymbol: - kind = GetIirKindOfNode(node) - if kind == nodes.Iir_Kind.Selected_Name: - name = GetNameOfNode(node) - prefixName = cls.GetLibrarySymbol(nodes.Get_Prefix(node)) - return PackageReferenceSymbol(node, name, prefixName) - else: - raise DOMException() - - @classmethod - def GetLibrarySymbol(cls, node: Iir) -> LibraryReferenceSymbol: - kind = GetIirKindOfNode(node) - if kind == nodes.Iir_Kind.Simple_Name: - name = GetNameOfNode(node) - return LibraryReferenceSymbol(node, name) - else: - raise DOMException() - @classmethod def parse(cls, useNode: Iir): - uses = [cls.GetPackageMemberSymbol(nodes.Get_Selected_Name(useNode))] + uses = [GetPackageMemberSymbol(nodes.Get_Selected_Name(useNode))] for use in utils.chain_iter(nodes.Get_Use_Clause_Chain(useNode)): - uses.append(cls.GetPackageMemberSymbol(nodes.Get_Selected_Name(use))) + uses.append(GetPackageMemberSymbol(nodes.Get_Selected_Name(use))) return cls(useNode, uses) @@ -328,11 +297,10 @@ class Context(VHDLModel_Context, DOMMixin): self, node: Iir, identifier: str, - libraryReferences: Iterable[LibraryClause] = None, - packageReferences: Iterable[UseClause] = None, + references: Iterable[Union[LibraryClause, UseClause]] = None, documentation: str = None, ): - super().__init__(identifier, libraryReferences, packageReferences, documentation) + super().__init__(identifier, references, documentation) DOMMixin.__init__(self, node) @classmethod @@ -347,7 +315,8 @@ class Context(VHDLModel_Context, DOMMixin): for item in utils.chain_iter(nodes.Get_Context_Items(contextNode)): kind = GetIirKindOfNode(item) if kind is nodes.Iir_Kind.Library_Clause: - names.append(SimpleName(item, GetNameOfNode(item))) + libraryIdentifier = GetNameOfNode(item) + names.append(LibraryReferenceSymbol(item, libraryIdentifier)) if nodes.Get_Has_Identifier_List(item): continue @@ -355,6 +324,8 @@ class Context(VHDLModel_Context, DOMMixin): names = [] elif kind is nodes.Iir_Kind.Use_Clause: items.append(UseClause.parse(item)) + elif kind is nodes.Iir_Kind.Context_Reference: + items.append(ContextReference.parse(item)) else: pos = Position.parse(item) raise DOMException(f"Unknown context item kind '{kind.name}' in context at line {pos.Line}.") diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 8bc1f34a0..87dd227a8 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -30,8 +30,11 @@ # # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ +from typing import Union + from pyTooling.Decorators import export +from pyGHDL.dom.Symbol import LibraryReferenceSymbol, PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol from pyVHDLModel.SyntaxModel import Mode from pyGHDL.libghdl import LibGHDLException, name_table, errorout_memory, files_map, file_comments @@ -134,3 +137,31 @@ def GetModeOfNode(node: Iir) -> Mode: return __MODE_TRANSLATION[nodes.Get_Mode(node)] except KeyError as ex: raise DOMException(f"Unknown mode '{ex.args[0]}'.") from ex + +def GetPackageMemberSymbol(node: Iir) -> Union[PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: + kind = GetIirKindOfNode(node) + prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) + if kind == nodes.Iir_Kind.Selected_Name: + name = GetNameOfNode(node) + return PackageMembersReferenceSymbol(node, name, prefixName) + elif kind == nodes.Iir_Kind.Selected_By_All_Name: + return AllPackageMembersReferenceSymbol(node, prefixName) + else: + raise DOMException() + +def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: + kind = GetIirKindOfNode(node) + if kind == nodes.Iir_Kind.Selected_Name: + name = GetNameOfNode(node) + prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) + return PackageReferenceSymbol(node, name, prefixName) + else: + raise DOMException() + +def GetLibrarySymbol(node: Iir) -> LibraryReferenceSymbol: + kind = GetIirKindOfNode(node) + if kind == nodes.Iir_Kind.Simple_Name: + name = GetNameOfNode(node) + return LibraryReferenceSymbol(node, name) + else: + raise DOMException() diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl new file mode 100644 index 000000000..1a40718aa --- /dev/null +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl @@ -0,0 +1,21 @@ +-- Author: Patrick Lehmann +-- License: MIT +-- +-- A generic counter module used in the StopWatch example. +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +-- Package with stop watch specific types. +package StopWatch_pkg is + subtype T_BCD is unsigned(3 downto 0); + type T_BCD_Vector is array(natural range <>) of T_BCD; + + type T_DIGIT_CONFIGURATION is record + Modulo : positive; + Dot : std_logic; + end record; + + type T_STOPWATCH_CONFIGURATION is array(natural range <>) of T_DIGIT_CONFIGURATION; +end package; diff --git a/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl new file mode 100644 index 000000000..e6551cffd --- /dev/null +++ b/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl @@ -0,0 +1,12 @@ +-- Author: Patrick Lehmann +-- License: MIT +-- +-- A generic counter module used in the StopWatch example. +-- +context StopWatch_ctx is + library IEEE; + use IEEE.std_logic_1164.all, + IEEE.numeric_std.all; + + use work.StopWatch_pkg.all; +end context; -- cgit v1.2.3 From fd6fc2a7d5f577802fd4622501af4d871536fc41 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 26 Dec 2022 10:49:23 +0100 Subject: More adjustments to new symbols. --- pyGHDL/dom/DesignUnit.py | 18 +++++++++--------- pyGHDL/dom/Symbol.py | 17 +++++++++++------ pyGHDL/dom/formatting/prettyprint.py | 2 +- 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 8ccdb91bb..054fe0e7b 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -77,7 +77,7 @@ from pyGHDL.dom._Translate import ( GetConcurrentStatementsFromChainedNodes, ) from pyGHDL.dom.Names import SimpleName -from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol +from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol @export @@ -171,8 +171,7 @@ class Architecture(VHDLModel_Architecture, DOMMixin): name = GetNameOfNode(architectureNode) documentation = GetDocumentationOfNode(architectureNode) entityNameNode = nodes.Get_Entity_Name(architectureNode) - entityName = GetNameOfNode(entityNameNode) - entitySymbol = EntitySymbol(entityNameNode, SimpleName(entityNameNode, entityName)) + entitySymbol = EntitySymbol(entityNameNode, GetNameOfNode(entityNameNode)) declaredItems = GetDeclaredItemsFromChainedNodes( nodes.Get_Declaration_Chain(architectureNode), "architecture", name ) @@ -245,23 +244,24 @@ class PackageBody(VHDLModel_PackageBody, DOMMixin): def __init__( self, node: Iir, - identifier: str, + packageSymbol: PackageSymbol, contextItems: Iterable[VHDLModel_ContextUnion] = None, declaredItems: Iterable = None, documentation: str = None, ): - super().__init__(identifier, contextItems, declaredItems, documentation) + super().__init__(packageSymbol, contextItems, declaredItems, documentation) DOMMixin.__init__(self, node) @classmethod def parse(cls, packageBodyNode: Iir, contextItems: Iterable[VHDLModel_ContextUnion]): - name = GetNameOfNode(packageBodyNode) + packageName = GetNameOfNode(packageBodyNode) + packageSymbol = PackageSymbol(packageBodyNode, packageName) documentation = GetDocumentationOfNode(packageBodyNode) - declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(packageBodyNode), "package", name) + declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(packageBodyNode), "package", packageName) # FIXME: read use clauses - return cls(packageBodyNode, name, contextItems, declaredItems, documentation) + return cls(packageBodyNode, packageSymbol, contextItems, declaredItems, documentation) @export @@ -297,7 +297,7 @@ class Context(VHDLModel_Context, DOMMixin): self, node: Iir, identifier: str, - references: Iterable[Union[LibraryClause, UseClause]] = None, + references: Iterable[Union[LibraryClause, UseClause, ContextReference]] = None, documentation: str = None, ): super().__init__(identifier, references, documentation) diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index ed1acb7b1..40d877c3f 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -59,6 +59,7 @@ from pyGHDL.dom.Range import Range @export class LibraryReferenceSymbol(VHDLModel_LibraryReferenceSymbol, DOMMixin): + @InheritDocString(VHDLModel_LibraryReferenceSymbol) def __init__(self, libraryNode: Iir, identifier: str): super().__init__(identifier) DOMMixin.__init__(self, libraryNode) @@ -66,6 +67,7 @@ class LibraryReferenceSymbol(VHDLModel_LibraryReferenceSymbol, DOMMixin): @export class PackageReferenceSymbol(VHDLModel_PackageReferenceSymbol, DOMMixin): + @InheritDocString(VHDLModel_PackageReferenceSymbol) def __init__(self, libraryNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): super().__init__(identifier, prefix) DOMMixin.__init__(self, libraryNode) @@ -73,6 +75,7 @@ class PackageReferenceSymbol(VHDLModel_PackageReferenceSymbol, DOMMixin): @export class PackageMembersReferenceSymbol(VHDLModel_PackageMembersReferenceSymbol, DOMMixin): + @InheritDocString(VHDLModel_PackageMembersReferenceSymbol) def __init__(self, libraryNode: Iir, identifier: str, prefix: PackageReferenceSymbol): super().__init__(identifier, prefix) DOMMixin.__init__(self, libraryNode) @@ -80,6 +83,7 @@ class PackageMembersReferenceSymbol(VHDLModel_PackageMembersReferenceSymbol, DOM @export class AllPackageMembersReferenceSymbol(VHDLModel_AllPackageMembersReferenceSymbol, DOMMixin): + @InheritDocString(VHDLModel_AllPackageMembersReferenceSymbol) def __init__(self, libraryNode: Iir, prefix: PackageReferenceSymbol): super().__init__(prefix) DOMMixin.__init__(self, libraryNode) @@ -87,6 +91,7 @@ class AllPackageMembersReferenceSymbol(VHDLModel_AllPackageMembersReferenceSymbo @export class ContextReferenceSymbol(VHDLModel_ContextReferenceSymbol, DOMMixin): + @InheritDocString(VHDLModel_ContextReferenceSymbol) def __init__(self, libraryNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): super().__init__(identifier, prefix) DOMMixin.__init__(self, libraryNode) @@ -95,24 +100,24 @@ class ContextReferenceSymbol(VHDLModel_ContextReferenceSymbol, DOMMixin): @export class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin): @InheritDocString(VHDLModel_EntitySymbol) - def __init__(self, node: Iir, entityName: SimpleName): - super().__init__(entityName) + def __init__(self, node: Iir, identifier: str): + super().__init__(identifier) DOMMixin.__init__(self, node) @export class ArchitectureSymbol(VHDLModel_ArchitectureSymbol, DOMMixin): @InheritDocString(VHDLModel_ArchitectureSymbol) - def __init__(self, node: Iir, architectureName: SimpleName): - super().__init__(architectureName) + def __init__(self, node: Iir, identifier: str, prefix: EntitySymbol): + super().__init__(identifier, prefix) DOMMixin.__init__(self, node) @export class PackageSymbol(VHDLModel_PackageSymbol, DOMMixin): @InheritDocString(VHDLModel_PackageSymbol) - def __init__(self, node: Iir, packageName: SimpleName): - super().__init__(packageName) + def __init__(self, node: Iir, identifier: str): + super().__init__(identifier) DOMMixin.__init__(self, node) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 7c99e1d87..29751b507 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -236,7 +236,7 @@ class PrettyPrint: f"{prefix} Position: {architecture.Position.Line}:{architecture.Position.Column}\n" f"{prefix} Documentation: {documentationFirstLine}" ) - buffer.append(f"{prefix} Entity: {architecture.Entity.SymbolName}") + buffer.append(f"{prefix} Entity: {architecture.Entity.Identifier}") buffer.append(f"{prefix} Declared:") for item in architecture.DeclaredItems: for line in self.formatDeclaredItems(item, level + 2): -- cgit v1.2.3 From f1059ae910767d5bb89244175d892a34e57fab63 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 26 Dec 2022 22:39:26 +0100 Subject: Bumped dependecy to pyVHDLModel and added analysis time measurements. --- pyGHDL/dom/NonStandard.py | 15 +++++++++++++++ pyGHDL/dom/requirements.txt | 2 +- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py index 64c34b527..579874bfc 100644 --- a/pyGHDL/dom/NonStandard.py +++ b/pyGHDL/dom/NonStandard.py @@ -111,6 +111,21 @@ class Design(VHDLModel_Design): if libghdl_analyze_init_status() != 0: raise LibGHDLException("Error initializing 'libghdl'.") + def LoadDefaultLibraries(self): + t1 = time.perf_counter() + + super().LoadStdLibrary() + super().LoadIEEELibrary() + + self._loadDefaultLibraryTime = time.perf_counter() - t1 + + def Analyze(self): + t1 = time.perf_counter() + + super().Analyze() + + self._analyzeTime = time.perf_counter() - t1 + @export class Library(VHDLModel_Library): diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt index 6b540d7b7..d274927cc 100644 --- a/pyGHDL/dom/requirements.txt +++ b/pyGHDL/dom/requirements.txt @@ -1,4 +1,4 @@ -r ../libghdl/requirements.txt -pyVHDLModel==0.18.0 +pyVHDLModel==0.19.0 #https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel -- cgit v1.2.3 From 78a439d9e8a220125895312162fcebe62863f261 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 26 Dec 2022 22:40:28 +0100 Subject: Replaced specific code with routines from pyVHDLModel. --- pyGHDL/cli/dom.py | 21 ++++++++++++++------- pyGHDL/dom/_Utils.py | 11 +++++++---- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/pyGHDL/cli/dom.py b/pyGHDL/cli/dom.py index 68bd33c34..7ca4a17da 100755 --- a/pyGHDL/cli/dom.py +++ b/pyGHDL/cli/dom.py @@ -299,16 +299,23 @@ class Application(LineTerminal, ArgParseMixin): ) ) - for library in self._design.Libraries.values(): - for entityName, architectures in library.Architectures.items(): - for entity in library.Entities: - if entity.Identifier == str(entityName): - for architecture in architectures: - entity.Architectures.append(architecture) - if not self._design.Documents: self.WriteFatal("No files processed at all.") + self._design.LoadDefaultLibraries() + self._design.Analyze() + self.WriteInfo( + dedent( + """\ + default library load time: {:5.3f} us + dependency analysis time: {:5.3f} us + """ + ).format( + self._design._loadDefaultLibraryTime * 10**6, + self._design._analyzeTime * 10**6, + ) + ) + PP = PrettyPrint() buffer = [] diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 87dd227a8..185f07bc4 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -41,7 +41,7 @@ from pyGHDL.libghdl import LibGHDLException, name_table, errorout_memory, files_ from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes, utils from pyGHDL.libghdl.vhdl.nodes import Null_Iir -from pyGHDL.dom import DOMException +from pyGHDL.dom import DOMException, Position __MODE_TRANSLATION = { nodes.Iir_Mode.In_Mode: Mode.In, @@ -138,6 +138,7 @@ def GetModeOfNode(node: Iir) -> Mode: except KeyError as ex: raise DOMException(f"Unknown mode '{ex.args[0]}'.") from ex + def GetPackageMemberSymbol(node: Iir) -> Union[PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: kind = GetIirKindOfNode(node) prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) @@ -147,7 +148,8 @@ def GetPackageMemberSymbol(node: Iir) -> Union[PackageMembersReferenceSymbol, Al elif kind == nodes.Iir_Kind.Selected_By_All_Name: return AllPackageMembersReferenceSymbol(node, prefixName) else: - raise DOMException() + raise DOMException(f"{kind.name} at {Position.parse(node)}") + def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: kind = GetIirKindOfNode(node) @@ -156,7 +158,8 @@ def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) return PackageReferenceSymbol(node, name, prefixName) else: - raise DOMException() + raise DOMException(f"{kind.name} at {Position.parse(node)}") + def GetLibrarySymbol(node: Iir) -> LibraryReferenceSymbol: kind = GetIirKindOfNode(node) @@ -164,4 +167,4 @@ def GetLibrarySymbol(node: Iir) -> LibraryReferenceSymbol: name = GetNameOfNode(node) return LibraryReferenceSymbol(node, name) else: - raise DOMException() + raise DOMException(f"{kind} at {Position.parse(node)}") -- cgit v1.2.3 From e2df91595f8647a81d53f164bf2f470fbbeb64dd Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 26 Dec 2022 22:41:06 +0100 Subject: Improved StopWatch testcase. --- testsuite/pyunit/dom/StopWatch.py | 58 +++++++++++++--------- .../dom/examples/StopWatch/StopWatch.ctx.vhdl | 22 +++----- .../dom/examples/StopWatch/Utilities.ctx.vhdl | 6 +-- .../dom/examples/StopWatch/Utilities.pkg.vhdl | 4 +- .../dom/examples/StopWatch/seg7_Encoder.vhdl | 7 +-- .../dom/examples/StopWatch/toplevel.Encoder.vhdl | 6 ++- 6 files changed, 51 insertions(+), 52 deletions(-) diff --git a/testsuite/pyunit/dom/StopWatch.py b/testsuite/pyunit/dom/StopWatch.py index 37b8293de..b733cd786 100644 --- a/testsuite/pyunit/dom/StopWatch.py +++ b/testsuite/pyunit/dom/StopWatch.py @@ -34,7 +34,7 @@ from pathlib import Path from unittest import TestCase from pyGHDL.dom.NonStandard import Design, Document - +from pyGHDL.dom.formatting.prettyprint import PrettyPrint if __name__ == "__main__": print("ERROR: you called a testcase declaration file as an executable module.") @@ -47,51 +47,56 @@ class Designs(TestCase): _sourceDirectory: Path = _root / "dom/examples/StopWatch" _packageFiles = ( - Path("Utilities.pkg.vhdl"), - Path("StopWatch.pkg.vhdl"), + ("lib_Utilities", Path("Utilities.pkg.vhdl")), + ("lib_Utilities", Path("Utilities.ctx.vhdl")), + ("lib_StopWatch", Path("StopWatch.pkg.vhdl")), + ("lib_StopWatch", Path("StopWatch.ctx.vhdl")), ) _encoderFiles = _packageFiles + ( - Path("seg7_Encoder.vhdl"), - Path("toplevel.Encoder.vhdl"), + ("lib_StopWatch", Path("seg7_Encoder.vhdl")), + ("lib_StopWatch", Path("toplevel.Encoder.vhdl")), ) _displayFiles = _packageFiles + ( - Path("Counter.vhdl"), - Path("seg7_Encoder.vhdl"), - Path("seg7_Display.vhdl"), - Path("toplevel.Display.vhdl"), + ("lib_StopWatch", Path("Counter.vhdl")), + ("lib_StopWatch", Path("seg7_Encoder.vhdl")), + ("lib_StopWatch", Path("seg7_Display.vhdl")), + ("lib_StopWatch", Path("toplevel.Display.vhdl")), ) _stopwatchFiles = _packageFiles + ( - Path("Counter.vhdl"), - Path("seg7_Encoder.vhdl"), - Path("seg7_Display.vhdl"), - Path("StopWatch.vhdl"), - Path("Debouncer.vhdl"), - Path("toplevel.StopWatch.vhdl"), + ("lib_Utilities", Path("Counter.vhdl")), + ("lib_StopWatch", Path("seg7_Encoder.vhdl")), + ("lib_StopWatch", Path("seg7_Display.vhdl")), + ("lib_StopWatch", Path("StopWatch.vhdl")), + ("lib_Utilities", Path("Debouncer.vhdl")), + ("lib_StopWatch", Path("toplevel.StopWatch.vhdl")), ) class Display(Designs): def test_Encoder(self): design = Design() - for file in self._encoderFiles: + for lib, file in self._encoderFiles: + library = design.GetLibrary(lib) document = Document(self._sourceDirectory / file) - design.Documents.append(document) + design.AddDocument(document, library) self.assertEqual(len(self._encoderFiles), len(design.Documents)) def test_Display(self): design = Design() - for file in self._displayFiles: + for lib, file in self._displayFiles: + library = design.GetLibrary(lib) document = Document(self._sourceDirectory / file) - design.Documents.append(document) + design.AddDocument(document, library) self.assertEqual(len(self._displayFiles), len(design.Documents)) def test_StopWatch(self): design = Design() - for file in self._stopwatchFiles: + for lib, file in self._stopwatchFiles: + library = design.GetLibrary(lib) document = Document(self._sourceDirectory / file) - design.Documents.append(document) + design.AddDocument(document, library) self.assertEqual(len(self._stopwatchFiles), len(design.Documents)) @@ -101,9 +106,16 @@ class CompileOrder(Designs): design = Design() design.LoadStdLibrary() design.LoadIEEELibrary() - library = design.GetLibrary("lib_StopWatch") - for file in self._encoderFiles: + for lib, file in self._encoderFiles: + library = design.GetLibrary(lib) document = Document(self._sourceDirectory / file) design.AddDocument(document, library) design.Analyze() + + PP = PrettyPrint() + buffer = [] + buffer.append("Design:") + for line in PP.formatDesign(design, 1): + buffer.append(line) + print("\n".join(buffer)) diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl index 1a40718aa..ea66f7597 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl @@ -1,21 +1,11 @@ -- Author: Patrick Lehmann -- License: MIT -- --- A generic counter module used in the StopWatch example. +-- undocumented -- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; +context StopWatch_ctx is + library lib_Utilities; + context lib_Utilities.Utilities_pkg; --- Package with stop watch specific types. -package StopWatch_pkg is - subtype T_BCD is unsigned(3 downto 0); - type T_BCD_Vector is array(natural range <>) of T_BCD; - - type T_DIGIT_CONFIGURATION is record - Modulo : positive; - Dot : std_logic; - end record; - - type T_STOPWATCH_CONFIGURATION is array(natural range <>) of T_DIGIT_CONFIGURATION; -end package; + use work.StopWatch_pkg.all; +end context; diff --git a/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl index e6551cffd..050682098 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl @@ -1,12 +1,12 @@ -- Author: Patrick Lehmann -- License: MIT -- --- A generic counter module used in the StopWatch example. +-- undocumented -- -context StopWatch_ctx is +context Utilities_ctx is library IEEE; use IEEE.std_logic_1164.all, IEEE.numeric_std.all; - use work.StopWatch_pkg.all; + use work.Utilities_pkg.all; end context; diff --git a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl index 16a40ccba..e15048dcf 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl @@ -9,7 +9,7 @@ use IEEE.numeric_std.all; -- Useful utility functions and types. -package Utilities is +package Utilities_pkg is type freq is range integer'low to integer'high units Hz; kHz = 1000 Hz; @@ -33,7 +33,7 @@ package Utilities is end package; -package body Utilities is +package body Utilities_pkg is function simulation return boolean is variable result : boolean := FALSE; begin diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl index 3742982be..88074c884 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl @@ -3,12 +3,7 @@ -- -- A generic counter module used in the StopWatch example. -- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.Utilities.all; -use work.StopWatch_pkg.all; +context work.StopWatch_ctx; -- Encoder that translates from 4-bit binary (BCD) to 7-segment code. diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl index 58294b67f..de18778a0 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl @@ -7,8 +7,10 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; -use work.StopWatch_pkg.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + +use lib_StopWatch.StopWatch_pkg.all; -- Toplevel module to demonstrate the translation of 4 slide-switches to 1 digit 7-segment display. -- cgit v1.2.3 From e38cf3c90f874db468b9943073b17635a1479e2f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 26 Dec 2022 23:17:22 +0100 Subject: Formatting by black. --- pyGHDL/dom/DesignUnit.py | 4 +++- pyGHDL/dom/NonStandard.py | 3 ++- pyGHDL/dom/_Utils.py | 7 ++++++- pyGHDL/dom/formatting/prettyprint.py | 7 ++----- 4 files changed, 13 insertions(+), 8 deletions(-) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 054fe0e7b..0b74940b2 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -257,7 +257,9 @@ class PackageBody(VHDLModel_PackageBody, DOMMixin): packageName = GetNameOfNode(packageBodyNode) packageSymbol = PackageSymbol(packageBodyNode, packageName) documentation = GetDocumentationOfNode(packageBodyNode) - declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(packageBodyNode), "package", packageName) + declaredItems = GetDeclaredItemsFromChainedNodes( + nodes.Get_Declaration_Chain(packageBodyNode), "package", packageName + ) # FIXME: read use clauses diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py index 579874bfc..e0b837c57 100644 --- a/pyGHDL/dom/NonStandard.py +++ b/pyGHDL/dom/NonStandard.py @@ -81,7 +81,8 @@ from pyGHDL.dom.DesignUnit import ( PackageInstantiation, LibraryClause, UseClause, - ContextReference, ) + ContextReference, +) from pyGHDL.dom.Symbol import LibraryReferenceSymbol from pyGHDL.dom.PSL import VerificationUnit, VerificationProperty, VerificationMode diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 185f07bc4..1b9dd06fb 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -34,7 +34,12 @@ from typing import Union from pyTooling.Decorators import export -from pyGHDL.dom.Symbol import LibraryReferenceSymbol, PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol +from pyGHDL.dom.Symbol import ( + LibraryReferenceSymbol, + PackageReferenceSymbol, + PackageMembersReferenceSymbol, + AllPackageMembersReferenceSymbol, +) from pyVHDLModel.SyntaxModel import Mode from pyGHDL.libghdl import LibGHDLException, name_table, errorout_memory, files_map, file_comments diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 29751b507..8510a91bd 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -114,7 +114,7 @@ class PrettyPrint: # def __init__(self): # self._buffer = [] - def CleanupDocumentationBlocks(self, documentationContent: str, level: int = 0): + def CleanupDocumentationBlocks(self, documentationContent: str, level: int = 0): prefix = " " * level if documentationContent is None: return prefix @@ -303,10 +303,7 @@ class PrettyPrint: buffer = [] prefix = " " * level documentationFirstLine = self.CleanupDocumentationBlocks(packageBody.Documentation) - buffer.append( - f"{prefix}- Name: {packageBody.Identifier}\n" - f"{prefix} Documentation: {documentationFirstLine}" - ) + buffer.append(f"{prefix}- Name: {packageBody.Identifier}\n{prefix} Documentation: {documentationFirstLine}") buffer.append(f"{prefix} Declared:") for item in packageBody.DeclaredItems: for line in self.formatDeclaredItems(item, level + 1): -- cgit v1.2.3 From 86a96a70103d0bd34213467c957144b2d27ae77f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 27 Dec 2022 12:28:40 +0100 Subject: Implemented GetContextSymbol and fixed how ContextReferenceSymbols are created. --- pyGHDL/dom/DesignUnit.py | 8 +++----- pyGHDL/dom/_Utils.py | 11 +++++++++++ 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 0b74940b2..8d9c677ad 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -69,7 +69,7 @@ from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, Position, DOMException -from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol +from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol, GetContextSymbol from pyGHDL.dom._Translate import ( GetGenericsFromChainedNodes, GetPortsFromChainedNodes, @@ -110,11 +110,9 @@ class ContextReference(VHDLModel_ContextReference, DOMMixin): @classmethod def parse(cls, contextNode: Iir): - from pyGHDL.dom._Translate import GetNameFromNode - - contexts = [ContextReferenceSymbol(GetNameFromNode(nodes.Get_Selected_Name(contextNode)))] + contexts = [GetContextSymbol(nodes.Get_Selected_Name(contextNode))] for context in utils.chain_iter(nodes.Get_Context_Reference_Chain(contextNode)): - contexts.append(ContextReferenceSymbol(GetNameFromNode(nodes.Get_Selected_Name(context)))) + contexts.append(GetContextSymbol(nodes.Get_Selected_Name(context))) return cls(contextNode, contexts) diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 1b9dd06fb..3803374f3 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -39,6 +39,7 @@ from pyGHDL.dom.Symbol import ( PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol, + ContextReferenceSymbol, ) from pyVHDLModel.SyntaxModel import Mode @@ -166,6 +167,16 @@ def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: raise DOMException(f"{kind.name} at {Position.parse(node)}") +def GetContextSymbol(node: Iir) -> ContextReferenceSymbol: + kind = GetIirKindOfNode(node) + if kind == nodes.Iir_Kind.Selected_Name: + name = GetNameOfNode(node) + prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) + return ContextReferenceSymbol(node, name, prefixName) + else: + raise DOMException(f"{kind.name} at {Position.parse(node)}") + + def GetLibrarySymbol(node: Iir) -> LibraryReferenceSymbol: kind = GetIirKindOfNode(node) if kind == nodes.Iir_Kind.Simple_Name: -- cgit v1.2.3 From a040eb775a5bcf7392d67595483d9dc6503e7075 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 27 Dec 2022 12:28:53 +0100 Subject: Improved prettyprint. --- pyGHDL/dom/formatting/prettyprint.py | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py index 8510a91bd..da26372c4 100644 --- a/pyGHDL/dom/formatting/prettyprint.py +++ b/pyGHDL/dom/formatting/prettyprint.py @@ -125,12 +125,12 @@ class PrettyPrint: def formatDesign(self, design: Design, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append(f"{prefix}Libraries:") + buffer.append(f"{prefix}Libraries ({len(design.Libraries)}):") for library in design.Libraries.values(): buffer.append(f"{prefix} - Name: {library.Identifier}") for line in self.formatLibrary(library, level + 2): buffer.append(line) - buffer.append(f"{prefix}Documents:") + buffer.append(f"{prefix}Documents ({len(design.Documents)}):") for document in design.Documents: buffer.append(f"{prefix} - Path: '{document.Path}':") for line in self.formatDocument(document, level + 2): @@ -141,19 +141,19 @@ class PrettyPrint: def formatLibrary(self, library: Library, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append(f"{prefix}Contexts:") + buffer.append(f"{prefix}Contexts ({len(library.Contexts)}):") for context in library.Contexts.values(): buffer.append(f"{prefix} - {context.Identifier}") - buffer.append(f"{prefix}Packages:") + buffer.append(f"{prefix}Packages ({len(library.Packages)}):") for package in library.Packages.values(): if isinstance(package, Package): buffer.append(f"{prefix} - {package.Identifier}") elif isinstance(package, PackageInstantiation): buffer.append(f"{prefix} - {package.Identifier} instantiate from {package.PackageReference}") - buffer.append(f"{prefix}Entities:") + buffer.append(f"{prefix}Entities ({len(library.Entities)}):") for entity in library.Entities.values(): buffer.append(f"{prefix} - {entity.Identifier}({', '.join([a.Identifier for a in entity.Architectures])})") - buffer.append(f"{prefix}Configurations:") + buffer.append(f"{prefix}Configurations ({len(library.Configurations)}):") for configuration in library.Configurations.values(): buffer.append(f"{prefix} - {configuration.Identifier}") @@ -162,11 +162,11 @@ class PrettyPrint: def formatDocument(self, document: Document, level: int = 0) -> StringBuffer: buffer = [] prefix = " " * level - buffer.append(f"{prefix}Contexts:") + buffer.append(f"{prefix}Contexts ({len(document.Contexts)}):") for context in document.Contexts.values(): for line in self.formatContext(context, level + 1): buffer.append(line) - buffer.append(f"{prefix}Packages:") + buffer.append(f"{prefix}Packages ({len(document.Packages)}):") for package in document.Packages.values(): if isinstance(package, Package): gen = self.formatPackage @@ -175,20 +175,20 @@ class PrettyPrint: for line in gen(package, level + 1): buffer.append(line) - buffer.append(f"{prefix}PackageBodies:") + buffer.append(f"{prefix}PackageBodies ({len(document.PackageBodies)}):") for packageBodies in document.PackageBodies.values(): for line in self.formatPackageBody(packageBodies, level + 1): buffer.append(line) - buffer.append(f"{prefix}Entities:") + buffer.append(f"{prefix}Entities ({len(document.Entities)}):") for entity in document.Entities.values(): for line in self.formatEntity(entity, level + 1): buffer.append(line) - buffer.append(f"{prefix}Architectures:") + buffer.append(f"{prefix}Architectures ({len(document.Architectures)}):") for architectures in document.Architectures.values(): for architecture in architectures.values(): for line in self.formatArchitecture(architecture, level + 1): buffer.append(line) - buffer.append(f"{prefix}Configurations:") + buffer.append(f"{prefix}Configurations ({len(document.Configurations)}):") for configuration in document.Configurations.values(): for line in self.formatConfiguration(configuration, level + 1): buffer.append(line) -- cgit v1.2.3 From 6ac6c1933ecf06ee908ac4e0f0ad27d532ba7d88 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 27 Dec 2022 22:42:47 +0100 Subject: Fixed glob pattern in DOM CLI test program. --- pyGHDL/cli/dom.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pyGHDL/cli/dom.py b/pyGHDL/cli/dom.py index 7ca4a17da..442ad6688 100755 --- a/pyGHDL/cli/dom.py +++ b/pyGHDL/cli/dom.py @@ -280,11 +280,11 @@ class Application(LineTerminal, ArgParseMixin): ) ) elif args.Directory is not None: - d: Path = args.Directory + d: Path = args.Directory.resolve() if not d.exists(): self.WriteError(f"Directory '{d!s}' does not exist.") - for file in d.glob("**/*.vhd?"): + for file in d.glob("**/*.vhd*"): self.WriteNormal(f"Parsing file '{file!s}'") document = self.addFile(file, "pretty") self.WriteInfo( -- cgit v1.2.3 From a525cd1f73760041f2d8c3dcc4f4e09eb024cff7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 27 Dec 2022 22:44:03 +0100 Subject: Fixed context and package names and their references in VHDL example code. --- testsuite/pyunit/dom/examples/StopWatch/Counter.vhdl | 2 +- testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl | 2 +- testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl | 2 +- testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl | 4 +++- testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl | 4 +++- testsuite/pyunit/dom/examples/StopWatch/toplevel.Display.vhdl | 4 +++- testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl | 2 +- testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.tb.vhdl | 7 ++++--- testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl | 4 +++- 9 files changed, 20 insertions(+), 11 deletions(-) diff --git a/testsuite/pyunit/dom/examples/StopWatch/Counter.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Counter.vhdl index 3ef284b98..b26a0fa09 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Counter.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Counter.vhdl @@ -7,7 +7,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +use work.Utilities_pkg.all; entity Counter is diff --git a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl index 18207c7f1..4e687da0b 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl @@ -7,7 +7,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +use work.Utilities_pkg.all; entity Debouncer is diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl index ea66f7597..dc89d5b3b 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl @@ -5,7 +5,7 @@ -- context StopWatch_ctx is library lib_Utilities; - context lib_Utilities.Utilities_pkg; + context lib_Utilities.Utilities_ctx; use work.StopWatch_pkg.all; end context; diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl index c7c9068ab..3d73fa0fa 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl @@ -7,7 +7,9 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + use work.StopWatch_pkg.all; diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl index c3771ba68..12e8e55aa 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl @@ -7,7 +7,9 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + use work.StopWatch_pkg.all; diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Display.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Display.vhdl index 67228a5ac..648ab81e4 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Display.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Display.vhdl @@ -7,7 +7,9 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + use work.StopWatch_pkg.all; diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl index de18778a0..17f7c6b19 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl @@ -10,7 +10,7 @@ use IEEE.numeric_std.all; library lib_Utilities; use lib_Utilities.Utilities_pkg.all; -use lib_StopWatch.StopWatch_pkg.all; +use work.StopWatch_pkg.all; -- Toplevel module to demonstrate the translation of 4 slide-switches to 1 digit 7-segment display. diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.tb.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.tb.vhdl index a334475c4..87cd75829 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.tb.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.tb.vhdl @@ -7,9 +7,10 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library lib_StopWatch; -use lib_StopWatch.Utilities.all; -use lib_StopWatch.StopWatch_pkg.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + +use work.StopWatch_pkg.all; entity toplevel_tb is diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl index 1c8547446..7bb6e9cd9 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl @@ -7,7 +7,9 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + use work.StopWatch_pkg.all; -- cgit v1.2.3 From 3b019ea6a8eac23ed3270a7112bd092526402211 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 27 Dec 2022 22:44:23 +0100 Subject: Fixed duplicate testcase name (Vital). --- testsuite/pyunit/dom/VHDLLibraries.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testsuite/pyunit/dom/VHDLLibraries.py b/testsuite/pyunit/dom/VHDLLibraries.py index 9de39b81b..c8a39ed23 100644 --- a/testsuite/pyunit/dom/VHDLLibraries.py +++ b/testsuite/pyunit/dom/VHDLLibraries.py @@ -85,7 +85,7 @@ def test_Synopsys(file): @mark.xfail(reason="Needs further investigations.") @mark.parametrize("file", [str(f.relative_to(_VITAL_ROOT)) for f in _VITAL_ROOT.glob("*.vhdl")]) -def test_Synopsys(file): +def test_Vital(file): filePath = _VITAL_ROOT / file lib = design.GetLibrary("vital") -- cgit v1.2.3 From 9cf69f324186932e4308e1ca0b19f563dab90e5e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 29 Dec 2022 23:16:27 +0100 Subject: Added Get***Symbol functions. Improved Symbol handling. --- pyGHDL/dom/Concurrent.py | 80 ++++++---------------- pyGHDL/dom/DesignUnit.py | 4 +- pyGHDL/dom/Symbol.py | 68 ++++++++++++------ pyGHDL/dom/_Translate.py | 1 + pyGHDL/dom/_Utils.py | 44 +++++++++--- .../dom/examples/StopWatch/seg7_Display.cfg.vhdl | 42 ++++++++++++ .../pyunit/dom/examples/StopWatch/sync_Bits.vhdl | 42 ++++++++++++ 7 files changed, 192 insertions(+), 89 deletions(-) create mode 100644 testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl create mode 100644 testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index df3e97a2a..0435792ef 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -35,6 +35,7 @@ from typing import Iterable from pyTooling.Decorators import export from pyGHDL.dom.Range import Range +from pyGHDL.dom.Symbol import ArchitectureSymbol, EntityInstantiationSymbol, ComponentInstantiationSymbol, ConfigurationInstantiationSymbol from pyVHDLModel.SyntaxModel import ( GenericAssociationItem as VHDLModel_GenericAssociationItem, PortAssociationItem as VHDLModel_PortAssociationItem, @@ -70,7 +71,7 @@ from pyVHDLModel.SyntaxModel import ( from pyGHDL.libghdl import Iir, utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, DOMException, Position -from pyGHDL.dom._Utils import GetNameOfNode +from pyGHDL.dom._Utils import GetNameOfNode, GetEntityInstantiationSymbol, GetComponentInstantiationSymbol, GetConfigurationInstantiationSymbol @export @@ -100,32 +101,22 @@ class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin): self, instantiationNode: Iir, label: str, - componentName: Name, + componentSymbol: ComponentInstantiationSymbol, genericAssociations: Iterable[AssociationItem] = None, portAssociations: Iterable[AssociationItem] = None, ): - super().__init__(label, componentName, genericAssociations, portAssociations) + super().__init__(label, componentSymbol, genericAssociations, portAssociations) DOMMixin.__init__(self, instantiationNode) @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ComponentInstantiation": - from pyGHDL.dom._Translate import ( - GetNameFromNode, - GetGenericMapAspect, - GetPortMapAspect, - ) + from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect - componentName = GetNameFromNode(instantiatedUnit) + componentSymbol = GetComponentInstantiationSymbol(instantiatedUnit) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) - return cls( - instantiationNode, - label, - componentName, - genericAssociations, - portAssociations, - ) + return cls(instantiationNode, label, componentSymbol, genericAssociations, portAssociations) @export @@ -134,41 +125,30 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): self, instantiationNode: Iir, label: str, - entityName: Name, - architectureName: Name = None, + entitySymbol: EntityInstantiationSymbol, + architectureSymbol: ArchitectureSymbol = None, # TODO: merge both symbols ? genericAssociations: Iterable[AssociationItem] = None, portAssociations: Iterable[AssociationItem] = None, ): - super().__init__(label, entityName, architectureName, genericAssociations, portAssociations) + super().__init__(label, entitySymbol, architectureSymbol, genericAssociations, portAssociations) DOMMixin.__init__(self, instantiationNode) @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation": - from pyGHDL.dom._Translate import ( - GetNameFromNode, - GetGenericMapAspect, - GetPortMapAspect, - ) + from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect entityId = nodes.Get_Entity_Name(instantiatedUnit) - entityName = GetNameFromNode(entityId) + entitySymbol = GetEntityInstantiationSymbol(entityId) - architectureName = None + architectureSymbol = None architectureId = nodes.Get_Architecture(instantiatedUnit) if architectureId != nodes.Null_Iir: - architectureName = GetNameOfNode(architectureId) + architectureSymbol = ArchitectureSymbol(GetNameOfNode(architectureId), entitySymbol) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) - return cls( - instantiationNode, - label, - entityName, - architectureName, - genericAssociations, - portAssociations, - ) + return cls(instantiationNode, label, entitySymbol, architectureSymbol, genericAssociations, portAssociations) @export @@ -177,34 +157,24 @@ class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin) self, instantiationNode: Iir, label: str, - configurationName: Name, + configurationSymbol: ConfigurationInstantiationSymbol, genericAssociations: Iterable[AssociationItem] = None, portAssociations: Iterable[AssociationItem] = None, ): - super().__init__(label, configurationName, genericAssociations, portAssociations) + super().__init__(label, configurationSymbol, genericAssociations, portAssociations) DOMMixin.__init__(self, instantiationNode) @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ConfigurationInstantiation": - from pyGHDL.dom._Translate import ( - GetNameFromNode, - GetGenericMapAspect, - GetPortMapAspect, - ) + from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect configurationId = nodes.Get_Configuration_Name(instantiatedUnit) - configurationName = GetNameFromNode(configurationId) + configurationSymbol = GetConfigurationInstantiationSymbol(configurationId) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) - return cls( - instantiationNode, - label, - configurationName, - genericAssociations, - portAssociations, - ) + return cls(instantiationNode, label, configurationSymbol, genericAssociations, portAssociations) @export @@ -221,10 +191,7 @@ class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin): @classmethod def parse(cls, blockNode: Iir, label: str) -> "ConcurrentBlockStatement": - from pyGHDL.dom._Translate import ( - GetDeclaredItemsFromChainedNodes, - GetConcurrentStatementsFromChainedNodes, - ) + from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes # genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) # portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) @@ -252,10 +219,7 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): @classmethod def parse(cls, processNode: Iir, label: str, hasSensitivityList: bool) -> "ProcessStatement": - from pyGHDL.dom._Translate import ( - GetDeclaredItemsFromChainedNodes, - GetSequentialStatementsFromChainedNodes, - ) + from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes sensitivityList = None if hasSensitivityList: diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 8d9c677ad..59b04a947 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -45,7 +45,6 @@ from pyTooling.Decorators import export from pyVHDLModel import ( ContextUnion as VHDLModel_ContextUnion, - EntityOrSymbol as VHDLModel_EntityOrSymbol, LibraryClause as VHDLModel_LibraryClause, UseClause as VHDLModel_UseClause, ContextReference as VHDLModel_ContextReference, @@ -76,7 +75,6 @@ from pyGHDL.dom._Translate import ( GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes, ) -from pyGHDL.dom.Names import SimpleName from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol @@ -155,7 +153,7 @@ class Architecture(VHDLModel_Architecture, DOMMixin): self, node: Iir, identifier: str, - entity: VHDLModel_EntityOrSymbol, + entity: EntitySymbol, contextItems: Iterable[VHDLModel_ContextUnion] = None, declaredItems: Iterable = None, statements: Iterable["ConcurrentStatement"] = None, diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index 40d877c3f..a9b919ccb 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -35,9 +35,6 @@ from typing import List, Iterator from pyTooling.Decorators import export, InheritDocString from pyVHDLModel.SyntaxModel import ( - EntitySymbol as VHDLModel_EntitySymbol, - ArchitectureSymbol as VHDLModel_ArchitectureSymbol, - PackageSymbol as VHDLModel_PackageSymbol, SimpleSubtypeSymbol as VHDLModel_SimpleSubtypeSymbol, ConstrainedScalarSubtypeSymbol as VHDLModel_ConstrainedScalarSubtypeSymbol, ConstrainedCompositeSubtypeSymbol as VHDLModel_ConstrainedCompositeSubtypeSymbol, @@ -50,76 +47,107 @@ from pyVHDLModel.SyntaxModel import ( PackageMembersReferenceSymbol as VHDLModel_PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol as VHDLModel_AllPackageMembersReferenceSymbol, ContextReferenceSymbol as VHDLModel_ContextReferenceSymbol, + EntityInstantiationSymbol as VHDLModel_EntityInstantiationSymbol, + ComponentInstantiationSymbol as VHDLModel_ComponentInstantiationSymbol, + ConfigurationInstantiationSymbol as VHDLModel_ConfigurationInstantiationSymbol, + EntitySymbol as VHDLModel_EntitySymbol, + ArchitectureSymbol as VHDLModel_ArchitectureSymbol, + PackageSymbol as VHDLModel_PackageSymbol, ) from pyGHDL.libghdl._types import Iir from pyGHDL.dom import DOMMixin -from pyGHDL.dom.Names import SimpleName from pyGHDL.dom.Range import Range @export class LibraryReferenceSymbol(VHDLModel_LibraryReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_LibraryReferenceSymbol) - def __init__(self, libraryNode: Iir, identifier: str): + def __init__(self, identifierNode: Iir, identifier: str): super().__init__(identifier) - DOMMixin.__init__(self, libraryNode) + DOMMixin.__init__(self, identifierNode) @export class PackageReferenceSymbol(VHDLModel_PackageReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_PackageReferenceSymbol) - def __init__(self, libraryNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): + def __init__(self, identifierNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): super().__init__(identifier, prefix) - DOMMixin.__init__(self, libraryNode) + DOMMixin.__init__(self, identifierNode) @export class PackageMembersReferenceSymbol(VHDLModel_PackageMembersReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_PackageMembersReferenceSymbol) - def __init__(self, libraryNode: Iir, identifier: str, prefix: PackageReferenceSymbol): + def __init__(self, identifierNode: Iir, identifier: str, prefix: PackageReferenceSymbol): super().__init__(identifier, prefix) - DOMMixin.__init__(self, libraryNode) + DOMMixin.__init__(self, identifierNode) @export class AllPackageMembersReferenceSymbol(VHDLModel_AllPackageMembersReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_AllPackageMembersReferenceSymbol) - def __init__(self, libraryNode: Iir, prefix: PackageReferenceSymbol): + def __init__(self, identifierNode: Iir, prefix: PackageReferenceSymbol): super().__init__(prefix) - DOMMixin.__init__(self, libraryNode) + DOMMixin.__init__(self, identifierNode) @export class ContextReferenceSymbol(VHDLModel_ContextReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_ContextReferenceSymbol) - def __init__(self, libraryNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): + def __init__(self, identifierNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): super().__init__(identifier, prefix) - DOMMixin.__init__(self, libraryNode) + DOMMixin.__init__(self, identifierNode) + + +@export +class EntityInstantiationSymbol(VHDLModel_EntityInstantiationSymbol, DOMMixin): + @InheritDocString(VHDLModel_EntityInstantiationSymbol) + def __init__(self, identifierNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): + super().__init__(identifier, prefix) + DOMMixin.__init__(self, identifierNode) + + +@export +class ComponentInstantiationSymbol(VHDLModel_ComponentInstantiationSymbol, DOMMixin): + @InheritDocString(VHDLModel_ComponentInstantiationSymbol) + def __init__(self, identifierNode: Iir, identifier: str): + super().__init__(identifier) + DOMMixin.__init__(self, identifierNode) + + +@export +class ConfigurationInstantiationSymbol(VHDLModel_ConfigurationInstantiationSymbol, DOMMixin): + @InheritDocString(VHDLModel_ConfigurationInstantiationSymbol) + def __init__(self, identifierNode: Iir, identifier: str): + super().__init__(identifier) + DOMMixin.__init__(self, identifierNode) @export class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin): @InheritDocString(VHDLModel_EntitySymbol) - def __init__(self, node: Iir, identifier: str): + def __init__(self, identifierNode: Iir, identifier: str): super().__init__(identifier) - DOMMixin.__init__(self, node) + DOMMixin.__init__(self, identifierNode) @export class ArchitectureSymbol(VHDLModel_ArchitectureSymbol, DOMMixin): @InheritDocString(VHDLModel_ArchitectureSymbol) - def __init__(self, node: Iir, identifier: str, prefix: EntitySymbol): + def __init__(self, identifierNode: Iir, identifier: str, prefix: EntitySymbol): super().__init__(identifier, prefix) - DOMMixin.__init__(self, node) + DOMMixin.__init__(self, identifierNode) @export class PackageSymbol(VHDLModel_PackageSymbol, DOMMixin): @InheritDocString(VHDLModel_PackageSymbol) - def __init__(self, node: Iir, identifier: str): + def __init__(self, identifierNode: Iir, identifier: str): super().__init__(identifier) - DOMMixin.__init__(self, node) + DOMMixin.__init__(self, identifierNode) +# TODO: |||| |||| +# TODO: VVVV old symbols VVVV @export class SimpleSubtypeSymbol(VHDLModel_SimpleSubtypeSymbol, DOMMixin): diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index f471824d3..6d3ced3ef 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -832,6 +832,7 @@ def GetConcurrentStatementsFromChainedNodes( elif kind == nodes.Iir_Kind.Component_Instantiation_Statement: instantiatedUnit = nodes.Get_Instantiated_Unit(statement) instantiatedUnitKind = GetIirKindOfNode(instantiatedUnit) + if instantiatedUnitKind == nodes.Iir_Kind.Entity_Aspect_Entity: yield EntityInstantiation.parse(statement, instantiatedUnit, label) elif instantiatedUnitKind == nodes.Iir_Kind.Entity_Aspect_Configuration: diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 3803374f3..20171b45c 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -39,7 +39,7 @@ from pyGHDL.dom.Symbol import ( PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol, - ContextReferenceSymbol, + ContextReferenceSymbol, EntityInstantiationSymbol, ComponentInstantiationSymbol, ConfigurationInstantiationSymbol, ) from pyVHDLModel.SyntaxModel import Mode @@ -145,6 +145,25 @@ def GetModeOfNode(node: Iir) -> Mode: raise DOMException(f"Unknown mode '{ex.args[0]}'.") from ex +def GetLibrarySymbol(node: Iir) -> LibraryReferenceSymbol: + kind = GetIirKindOfNode(node) + if kind == nodes.Iir_Kind.Simple_Name: + name = GetNameOfNode(node) + return LibraryReferenceSymbol(node, name) + else: + raise DOMException(f"{kind} at {Position.parse(node)}") + + +def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: + kind = GetIirKindOfNode(node) + if kind == nodes.Iir_Kind.Selected_Name: + name = GetNameOfNode(node) + prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) + return PackageReferenceSymbol(node, name, prefixName) + else: + raise DOMException(f"{kind.name} at {Position.parse(node)}") + + def GetPackageMemberSymbol(node: Iir) -> Union[PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: kind = GetIirKindOfNode(node) prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) @@ -157,30 +176,39 @@ def GetPackageMemberSymbol(node: Iir) -> Union[PackageMembersReferenceSymbol, Al raise DOMException(f"{kind.name} at {Position.parse(node)}") -def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: +def GetContextSymbol(node: Iir) -> ContextReferenceSymbol: kind = GetIirKindOfNode(node) if kind == nodes.Iir_Kind.Selected_Name: name = GetNameOfNode(node) prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) - return PackageReferenceSymbol(node, name, prefixName) + return ContextReferenceSymbol(node, name, prefixName) else: raise DOMException(f"{kind.name} at {Position.parse(node)}") -def GetContextSymbol(node: Iir) -> ContextReferenceSymbol: +def GetEntityInstantiationSymbol(node: Iir) -> EntityInstantiationSymbol: kind = GetIirKindOfNode(node) if kind == nodes.Iir_Kind.Selected_Name: name = GetNameOfNode(node) prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) - return ContextReferenceSymbol(node, name, prefixName) + return EntityInstantiationSymbol(node, name, prefixName) else: raise DOMException(f"{kind.name} at {Position.parse(node)}") -def GetLibrarySymbol(node: Iir) -> LibraryReferenceSymbol: +def GetComponentInstantiationSymbol(node: Iir) -> ComponentInstantiationSymbol: kind = GetIirKindOfNode(node) if kind == nodes.Iir_Kind.Simple_Name: name = GetNameOfNode(node) - return LibraryReferenceSymbol(node, name) + return ComponentInstantiationSymbol(node, name) else: - raise DOMException(f"{kind} at {Position.parse(node)}") + raise DOMException(f"{kind.name} at {Position.parse(node)}") + + +def GetConfigurationInstantiationSymbol(node: Iir) -> ConfigurationInstantiationSymbol: + kind = GetIirKindOfNode(node) + if kind == nodes.Iir_Kind.Simple_Name: + name = GetNameOfNode(node) + return ConfigurationInstantiationSymbol(node, name) + else: + raise DOMException(f"{kind.name} at {Position.parse(node)}") diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl new file mode 100644 index 000000000..88074c884 --- /dev/null +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl @@ -0,0 +1,42 @@ +-- Author: Patrick Lehmann +-- License: MIT +-- +-- A generic counter module used in the StopWatch example. +-- +context work.StopWatch_ctx; + + +-- Encoder that translates from 4-bit binary (BCD) to 7-segment code. +entity seg7_Encoder is + port ( + BCDValue : in T_BCD; + Dot : in std_logic := '0'; + + Seg7Code : out std_logic_vector(7 downto 0) + ); +end entity; + + +architecture rtl of seg7_Encoder is + +begin + process(BCDValue, Dot) + variable temp : std_logic_vector(6 downto 0); + begin + case BCDValue is -- segments: GFEDCBA -- Segment Pos. Index Pos. + when x"0" => temp := "0111111"; -- + when x"1" => temp := "0000110"; -- + when x"2" => temp := "1011011"; -- AAA 000 + when x"3" => temp := "1001111"; -- F B 5 1 + when x"4" => temp := "1100110"; -- F B 5 1 + when x"5" => temp := "1101101"; -- GGG 666 + when x"6" => temp := "1111101"; -- E C 4 2 + when x"7" => temp := "0000111"; -- E C 4 2 + when x"8" => temp := "1111111"; -- DDD DOT 333 7 + when x"9" => temp := "1101111"; -- + when others => temp := "XXXXXXX"; -- + end case; + + Seg7Code <= Dot & temp; + end process; +end architecture; diff --git a/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl b/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl new file mode 100644 index 000000000..88074c884 --- /dev/null +++ b/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl @@ -0,0 +1,42 @@ +-- Author: Patrick Lehmann +-- License: MIT +-- +-- A generic counter module used in the StopWatch example. +-- +context work.StopWatch_ctx; + + +-- Encoder that translates from 4-bit binary (BCD) to 7-segment code. +entity seg7_Encoder is + port ( + BCDValue : in T_BCD; + Dot : in std_logic := '0'; + + Seg7Code : out std_logic_vector(7 downto 0) + ); +end entity; + + +architecture rtl of seg7_Encoder is + +begin + process(BCDValue, Dot) + variable temp : std_logic_vector(6 downto 0); + begin + case BCDValue is -- segments: GFEDCBA -- Segment Pos. Index Pos. + when x"0" => temp := "0111111"; -- + when x"1" => temp := "0000110"; -- + when x"2" => temp := "1011011"; -- AAA 000 + when x"3" => temp := "1001111"; -- F B 5 1 + when x"4" => temp := "1100110"; -- F B 5 1 + when x"5" => temp := "1101101"; -- GGG 666 + when x"6" => temp := "1111101"; -- E C 4 2 + when x"7" => temp := "0000111"; -- E C 4 2 + when x"8" => temp := "1111111"; -- DDD DOT 333 7 + when x"9" => temp := "1101111"; -- + when others => temp := "XXXXXXX"; -- + end case; + + Seg7Code <= Dot & temp; + end process; +end architecture; -- cgit v1.2.3 From 7ae0931d3e6733ceb76f1d884e282d7d6b5fb489 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 29 Dec 2022 23:18:42 +0100 Subject: Improved VHDL example project. --- testsuite/pyunit/dom/StopWatch.py | 3 ++ .../pyunit/dom/examples/StopWatch/Debouncer.vhdl | 18 ++++++++- .../dom/examples/StopWatch/StopWatch.pkg.vhdl | 12 ++++++ .../dom/examples/StopWatch/Utilities.pkg.vhdl | 15 ++++++++ .../dom/examples/StopWatch/seg7_Display.cfg.vhdl | 40 ++++--------------- .../dom/examples/StopWatch/seg7_Display.vhdl | 2 +- .../pyunit/dom/examples/StopWatch/sync_Bits.vhdl | 45 ++++++++++------------ .../dom/examples/StopWatch/toplevel.StopWatch.vhdl | 4 +- 8 files changed, 77 insertions(+), 62 deletions(-) diff --git a/testsuite/pyunit/dom/StopWatch.py b/testsuite/pyunit/dom/StopWatch.py index b733cd786..6301eb1df 100644 --- a/testsuite/pyunit/dom/StopWatch.py +++ b/testsuite/pyunit/dom/StopWatch.py @@ -60,13 +60,16 @@ class Designs(TestCase): ("lib_StopWatch", Path("Counter.vhdl")), ("lib_StopWatch", Path("seg7_Encoder.vhdl")), ("lib_StopWatch", Path("seg7_Display.vhdl")), + ("lib_StopWatch", Path("seg7_Display.cfg.vhdl")), ("lib_StopWatch", Path("toplevel.Display.vhdl")), ) _stopwatchFiles = _packageFiles + ( ("lib_Utilities", Path("Counter.vhdl")), ("lib_StopWatch", Path("seg7_Encoder.vhdl")), ("lib_StopWatch", Path("seg7_Display.vhdl")), + ("lib_StopWatch", Path("seg7_Display.cfg.vhdl")), ("lib_StopWatch", Path("StopWatch.vhdl")), + ("lib_Utilities", Path("sync_Bits.vhdl")), ("lib_Utilities", Path("Debouncer.vhdl")), ("lib_StopWatch", Path("toplevel.StopWatch.vhdl")), ) diff --git a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl index 4e687da0b..ef1474164 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl @@ -15,7 +15,8 @@ entity Debouncer is CLOCK_PERIOD : time := 10 ns; DEBOUNCE_TIME : time := 3 ms; - BITS : positive + BITS : positive; + INPUT_SYNC : boolean := true ); port ( Clock : in std_logic; @@ -29,12 +30,27 @@ architecture rtl of Debouncer is constant DEBOUNCE_COUNTER_MAX : positive := DEBOUNCE_TIME / (CLOCK_PERIOD* ite(IS_SIMULATION, 20, 1)); constant DEBOUNCE_COUNTER_BITS : positive := log2(DEBOUNCE_COUNTER_MAX); + signal Input_sync : Input'subtype; begin assert false report "CLOCK_PERIOD: " & time'image(CLOCK_PERIOD); assert false report "DEBOUNCE_TIME: " & time'image(DEBOUNCE_TIME); --assert false report "DEBOUNCE_COUNTER_MAX: " & to_string(10 ns); --assert false report "INTEGER'high: " & integer'image(integer'high); + genSync: if INPUT_SYNC generate + sync: entity work.sync_Bits + generic map ( + BITS => BITS + ) + port map ( + Clock => Clock, + Input => Input, + Output => Input_sync + ); + else generate + Input_sync <= Input; + end generate; + genBits: for i in Input'range generate signal DebounceCounter : signed(DEBOUNCE_COUNTER_BITS downto 0) := to_signed(DEBOUNCE_COUNTER_MAX - 3, DEBOUNCE_COUNTER_BITS + 1); begin diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl index 1a40718aa..f67f99c72 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl @@ -18,4 +18,16 @@ package StopWatch_pkg is end record; type T_STOPWATCH_CONFIGURATION is array(natural range <>) of T_DIGIT_CONFIGURATION; + + -- Encoder that translates from 4-bit binary (BCD) to 7-segment code. + -- + -- In addition, an optional dot input is supported. + component seg7_Encoder is + port ( + BCDValue : in T_BCD; + Dot : in std_logic := '0'; + + Seg7Code : out std_logic_vector(7 downto 0) + ); + end component; end package; diff --git a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl index e15048dcf..6231261c0 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl @@ -30,6 +30,21 @@ package Utilities_pkg is function to_index(value : unsigned; max : positive) return natural; function to_index(value : natural; max : positive) return natural; + + component Debouncer is + generic ( + CLOCK_PERIOD : time := 10 ns; + DEBOUNCE_TIME : time := 3 ms; + + BITS : positive + ); + port ( + Clock : in std_logic; + + Input : in std_logic_vector(BITS - 1 downto 0); + Output : out std_logic_vector(BITS - 1 downto 0) := (others => '0') + ); + end component; end package; diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl index 88074c884..63d0c5e60 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl @@ -7,36 +7,10 @@ context work.StopWatch_ctx; -- Encoder that translates from 4-bit binary (BCD) to 7-segment code. -entity seg7_Encoder is - port ( - BCDValue : in T_BCD; - Dot : in std_logic := '0'; - - Seg7Code : out std_logic_vector(7 downto 0) - ); -end entity; - - -architecture rtl of seg7_Encoder is - -begin - process(BCDValue, Dot) - variable temp : std_logic_vector(6 downto 0); - begin - case BCDValue is -- segments: GFEDCBA -- Segment Pos. Index Pos. - when x"0" => temp := "0111111"; -- - when x"1" => temp := "0000110"; -- - when x"2" => temp := "1011011"; -- AAA 000 - when x"3" => temp := "1001111"; -- F B 5 1 - when x"4" => temp := "1100110"; -- F B 5 1 - when x"5" => temp := "1101101"; -- GGG 666 - when x"6" => temp := "1111101"; -- E C 4 2 - when x"7" => temp := "0000111"; -- E C 4 2 - when x"8" => temp := "1111111"; -- DDD DOT 333 7 - when x"9" => temp := "1101111"; -- - when others => temp := "XXXXXXX"; -- - end case; - - Seg7Code <= Dot & temp; - end process; -end architecture; +configuration seg7_Display_cfg of seg7_Display is + for rtl + for enc : seg7_Encoder + use entity work.seg7_Encoder(rtl); + end for; + end for; +end configuration; diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl index 12e8e55aa..da21075cf 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl @@ -79,7 +79,7 @@ begin Dot <= DotValues(to_index(Digit_Select, DotValues'high)); -- 7-segment encoder - enc: entity work.seg7_Encoder + enc: configuration seg7_Encoder port map ( BCDValue => Digit, Dot => Dot, diff --git a/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl b/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl index 88074c884..499305ec7 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl @@ -1,42 +1,37 @@ -- Author: Patrick Lehmann -- License: MIT -- --- A generic counter module used in the StopWatch example. +-- A generic multi-FF synchronizer. -- -context work.StopWatch_ctx; +library ieee; +use ieee.std_logic_1164.all; --- Encoder that translates from 4-bit binary (BCD) to 7-segment code. -entity seg7_Encoder is +-- Multi-stage FF synchronizer +entity sync_Bits is + generic ( + BITS : positive := 1; + STAGES : positive range 2 to 5 := 3 + ); port ( - BCDValue : in T_BCD; - Dot : in std_logic := '0'; + Clock : in std_logic; - Seg7Code : out std_logic_vector(7 downto 0) + Input : in std_logic_vector(BITS - 1 downto 0); + output : in std_logic_vector(BITS - 1 downto 0) ); end entity; -architecture rtl of seg7_Encoder is +architecture rtl of sync_Bits is begin - process(BCDValue, Dot) - variable temp : std_logic_vector(6 downto 0); + gen : for i in Input'range generate + signal meta : std_logic := '0'; + signal ffs : std_logic_vector(STAGES - 1 downto 1) := (others => '0'); begin - case BCDValue is -- segments: GFEDCBA -- Segment Pos. Index Pos. - when x"0" => temp := "0111111"; -- - when x"1" => temp := "0000110"; -- - when x"2" => temp := "1011011"; -- AAA 000 - when x"3" => temp := "1001111"; -- F B 5 1 - when x"4" => temp := "1100110"; -- F B 5 1 - when x"5" => temp := "1101101"; -- GGG 666 - when x"6" => temp := "1111101"; -- E C 4 2 - when x"7" => temp := "0000111"; -- E C 4 2 - when x"8" => temp := "1111111"; -- DDD DOT 333 7 - when x"9" => temp := "1101111"; -- - when others => temp := "XXXXXXX"; -- - end case; + meta <= Input(i) when rising_edge(Clock); + ffs <= (ffs(ffs'left downto 1) & meta) when rising_edge(Clock); - Seg7Code <= Dot & temp; - end process; + Output(i) <= ffs(ffs'left); + end generate; end architecture; diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl index 7bb6e9cd9..08046e2cc 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl @@ -59,7 +59,7 @@ begin Board_Reset <= not NexysA7_GPIO_Button_Reset_n; -- Debounce input signals - deb: entity work.Debouncer + deb: component Debouncer generic map ( CLOCK_PERIOD => CLOCK_PERIOD, BITS => 2 @@ -100,7 +100,7 @@ begin ); -- 7-segment display - display: entity work.seg7_Display + display: configuration seg7_Display_cfg generic map ( CLOCK_PERIOD => CLOCK_PERIOD, DIGITS => Digits'length -- cgit v1.2.3 From a32e651834af5745c7b1c709ff81a685af379970 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 30 Dec 2022 09:44:48 +0100 Subject: Bumped dependency to pyVHDLModel to v0.20.0 --- pyGHDL/dom/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt index d274927cc..a04360ab4 100644 --- a/pyGHDL/dom/requirements.txt +++ b/pyGHDL/dom/requirements.txt @@ -1,4 +1,4 @@ -r ../libghdl/requirements.txt -pyVHDLModel==0.19.0 +pyVHDLModel==0.20.0 #https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel -- cgit v1.2.3 From 4d95dd3c74785a8ac5d2a6af112d9fb12dd36b48 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 30 Dec 2022 12:46:41 +0100 Subject: Fixed handling of Use clauses in packages. --- pyGHDL/dom/_Utils.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 20171b45c..bc1841990 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -156,21 +156,24 @@ def GetLibrarySymbol(node: Iir) -> LibraryReferenceSymbol: def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: kind = GetIirKindOfNode(node) + name = GetNameOfNode(node) if kind == nodes.Iir_Kind.Selected_Name: - name = GetNameOfNode(node) prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) return PackageReferenceSymbol(node, name, prefixName) + elif kind == nodes.Iir_Kind.Simple_Name: + return PackageReferenceSymbol(node, name, None) else: raise DOMException(f"{kind.name} at {Position.parse(node)}") -def GetPackageMemberSymbol(node: Iir) -> Union[PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: +def GetPackageMemberSymbol(node: Iir) -> Union[PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: kind = GetIirKindOfNode(node) prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) if kind == nodes.Iir_Kind.Selected_Name: name = GetNameOfNode(node) return PackageMembersReferenceSymbol(node, name, prefixName) elif kind == nodes.Iir_Kind.Selected_By_All_Name: + prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) return AllPackageMembersReferenceSymbol(node, prefixName) else: raise DOMException(f"{kind.name} at {Position.parse(node)}") -- cgit v1.2.3 From 2940e1679a78c513cd67706211efd3cb68cf0f0d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 30 Dec 2022 13:37:08 +0100 Subject: Bumped dependency to pyVHDLModel to v0.20.2 --- pyGHDL/dom/DesignUnit.py | 4 ++-- pyGHDL/dom/requirements.txt | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 59b04a947..28a5dc0b6 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -48,7 +48,7 @@ from pyVHDLModel import ( LibraryClause as VHDLModel_LibraryClause, UseClause as VHDLModel_UseClause, ContextReference as VHDLModel_ContextReference, - Name, + Name, ContextUnion, ) from pyVHDLModel.SyntaxModel import ( Entity as VHDLModel_Entity, @@ -295,7 +295,7 @@ class Context(VHDLModel_Context, DOMMixin): self, node: Iir, identifier: str, - references: Iterable[Union[LibraryClause, UseClause, ContextReference]] = None, + references: Iterable[ContextUnion] = None, documentation: str = None, ): super().__init__(identifier, references, documentation) diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt index a04360ab4..90c229354 100644 --- a/pyGHDL/dom/requirements.txt +++ b/pyGHDL/dom/requirements.txt @@ -1,4 +1,4 @@ -r ../libghdl/requirements.txt -pyVHDLModel==0.20.0 +pyVHDLModel==0.20.2 #https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel -- cgit v1.2.3 From 882563d217d364d38a362d39bc34b7a6f16ce726 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 30 Dec 2022 13:52:27 +0100 Subject: Formatting by black. --- pyGHDL/dom/Concurrent.py | 16 +++++++++++++--- pyGHDL/dom/DesignUnit.py | 3 ++- pyGHDL/dom/Symbol.py | 2 ++ pyGHDL/dom/_Utils.py | 9 +++++++-- 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 0435792ef..8dcec9bdb 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -35,7 +35,12 @@ from typing import Iterable from pyTooling.Decorators import export from pyGHDL.dom.Range import Range -from pyGHDL.dom.Symbol import ArchitectureSymbol, EntityInstantiationSymbol, ComponentInstantiationSymbol, ConfigurationInstantiationSymbol +from pyGHDL.dom.Symbol import ( + ArchitectureSymbol, + EntityInstantiationSymbol, + ComponentInstantiationSymbol, + ConfigurationInstantiationSymbol, +) from pyVHDLModel.SyntaxModel import ( GenericAssociationItem as VHDLModel_GenericAssociationItem, PortAssociationItem as VHDLModel_PortAssociationItem, @@ -71,7 +76,12 @@ from pyVHDLModel.SyntaxModel import ( from pyGHDL.libghdl import Iir, utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, DOMException, Position -from pyGHDL.dom._Utils import GetNameOfNode, GetEntityInstantiationSymbol, GetComponentInstantiationSymbol, GetConfigurationInstantiationSymbol +from pyGHDL.dom._Utils import ( + GetNameOfNode, + GetEntityInstantiationSymbol, + GetComponentInstantiationSymbol, + GetConfigurationInstantiationSymbol, +) @export @@ -126,7 +136,7 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): instantiationNode: Iir, label: str, entitySymbol: EntityInstantiationSymbol, - architectureSymbol: ArchitectureSymbol = None, # TODO: merge both symbols ? + architectureSymbol: ArchitectureSymbol = None, # TODO: merge both symbols ? genericAssociations: Iterable[AssociationItem] = None, portAssociations: Iterable[AssociationItem] = None, ): diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 28a5dc0b6..881a7f2eb 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -48,7 +48,8 @@ from pyVHDLModel import ( LibraryClause as VHDLModel_LibraryClause, UseClause as VHDLModel_UseClause, ContextReference as VHDLModel_ContextReference, - Name, ContextUnion, + Name, + ContextUnion, ) from pyVHDLModel.SyntaxModel import ( Entity as VHDLModel_Entity, diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index a9b919ccb..76f794650 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -146,9 +146,11 @@ class PackageSymbol(VHDLModel_PackageSymbol, DOMMixin): super().__init__(identifier) DOMMixin.__init__(self, identifierNode) + # TODO: |||| |||| # TODO: VVVV old symbols VVVV + @export class SimpleSubtypeSymbol(VHDLModel_SimpleSubtypeSymbol, DOMMixin): def __init__(self, node: Iir, subtypeName: Name): diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index bc1841990..09f336c03 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -39,7 +39,10 @@ from pyGHDL.dom.Symbol import ( PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol, - ContextReferenceSymbol, EntityInstantiationSymbol, ComponentInstantiationSymbol, ConfigurationInstantiationSymbol, + ContextReferenceSymbol, + EntityInstantiationSymbol, + ComponentInstantiationSymbol, + ConfigurationInstantiationSymbol, ) from pyVHDLModel.SyntaxModel import Mode @@ -166,7 +169,9 @@ def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: raise DOMException(f"{kind.name} at {Position.parse(node)}") -def GetPackageMemberSymbol(node: Iir) -> Union[PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: +def GetPackageMemberSymbol( + node: Iir, +) -> Union[PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: kind = GetIirKindOfNode(node) prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) if kind == nodes.Iir_Kind.Selected_Name: -- cgit v1.2.3