From 931ee6aa4161cecc46f0370623415116cf1a1d69 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 1 Feb 2020 11:23:09 +0100
Subject: testsuite/synth: add more tests for #1122

---
 testsuite/synth/dff02/dff08a.vhdl    | 26 ++++++++++++++
 testsuite/synth/dff02/dff08b.vhdl    | 26 ++++++++++++++
 testsuite/synth/dff02/dff08c.vhdl    | 27 +++++++++++++++
 testsuite/synth/dff02/dff08d.vhdl    | 25 ++++++++++++++
 testsuite/synth/dff02/tb_dff08a.vhdl | 64 ++++++++++++++++++++++++++++++++++
 testsuite/synth/dff02/tb_dff08b.vhdl | 67 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/dff02/tb_dff08c.vhdl | 67 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/dff02/tb_dff08d.vhdl | 55 +++++++++++++++++++++++++++++
 testsuite/synth/dff02/testsuite.sh   |  2 +-
 9 files changed, 358 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/dff02/dff08a.vhdl
 create mode 100644 testsuite/synth/dff02/dff08b.vhdl
 create mode 100644 testsuite/synth/dff02/dff08c.vhdl
 create mode 100644 testsuite/synth/dff02/dff08d.vhdl
 create mode 100644 testsuite/synth/dff02/tb_dff08a.vhdl
 create mode 100644 testsuite/synth/dff02/tb_dff08b.vhdl
 create mode 100644 testsuite/synth/dff02/tb_dff08c.vhdl
 create mode 100644 testsuite/synth/dff02/tb_dff08d.vhdl

diff --git a/testsuite/synth/dff02/dff08a.vhdl b/testsuite/synth/dff02/dff08a.vhdl
new file mode 100644
index 000000000..43bb15135
--- /dev/null
+++ b/testsuite/synth/dff02/dff08a.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff08a is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic;
+        en : std_logic;
+        rst : std_logic);
+end dff08a;
+
+architecture behav of dff08a is
+  signal p : std_logic_vector(7 downto 0);
+begin
+  process (clk, rst) is
+  begin
+    if en = '0' then
+      null;
+    elsif rst = '1' then
+      p <= x"00";
+    elsif rising_edge (clk) then
+      p <= d;
+    end if;
+  end process;
+  q <= p;
+end behav;
diff --git a/testsuite/synth/dff02/dff08b.vhdl b/testsuite/synth/dff02/dff08b.vhdl
new file mode 100644
index 000000000..55b8f4dcb
--- /dev/null
+++ b/testsuite/synth/dff02/dff08b.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff08b is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic;
+        en : std_logic;
+        rst : std_logic);
+end dff08b;
+
+architecture behav of dff08b is
+  signal p : std_logic_vector(7 downto 0) := x"aa";
+begin
+  process (clk, rst) is
+  begin
+    if en = '0' then
+      null;
+    elsif rst = '1' then
+      p <= x"00";
+    elsif rising_edge (clk) then
+      p <= d;
+    end if;
+  end process;
+  q <= p;
+end behav;
diff --git a/testsuite/synth/dff02/dff08c.vhdl b/testsuite/synth/dff02/dff08c.vhdl
new file mode 100644
index 000000000..70626168c
--- /dev/null
+++ b/testsuite/synth/dff02/dff08c.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff08c is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic;
+        en : std_logic;
+        rst : std_logic);
+end dff08c;
+
+architecture behav of dff08c is
+  constant c : std_logic_vector(7 downto 0) := x"aa";
+  signal p : std_logic_vector(7 downto 0) := c;
+begin
+  process (clk, rst) is
+  begin
+    if en = '0' then
+      null;
+    elsif rst = '1' then
+      p <= c;
+    elsif rising_edge (clk) then
+      p <= d;
+    end if;
+  end process;
+  q <= p;
+end behav;
diff --git a/testsuite/synth/dff02/dff08d.vhdl b/testsuite/synth/dff02/dff08d.vhdl
new file mode 100644
index 000000000..d17b9d602
--- /dev/null
+++ b/testsuite/synth/dff02/dff08d.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff08d is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic;
+        en : std_logic;
+        rst : std_logic);
+end dff08d;
+
+architecture behav of dff08d is
+  constant c : std_logic_vector(7 downto 0) := x"aa";
+  signal p : std_logic_vector(7 downto 0) := c;
+begin
+  process (clk, rst) is
+  begin
+    if rst = '1' then
+      p <= c;
+    elsif rising_edge (clk) then
+      p <= d;
+    end if;
+  end process;
+  q <= p;
+end behav;
diff --git a/testsuite/synth/dff02/tb_dff08a.vhdl b/testsuite/synth/dff02/tb_dff08a.vhdl
new file mode 100644
index 000000000..cd1bacb6d
--- /dev/null
+++ b/testsuite/synth/dff02/tb_dff08a.vhdl
@@ -0,0 +1,64 @@
+entity tb_dff08a is
+end tb_dff08a;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff08a is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal en : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff08a
+    port map (
+      q => dout,
+      d => din,
+      en => en,
+      clk => clk,
+      rst => rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    en <= '1';
+    pulse;
+    assert dout = x"00" severity failure;
+
+    rst <= '0';
+    din <= x"38";
+    pulse;
+    assert dout = x"38" severity failure;
+
+    din <= x"af";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '0';
+    din <= x"b3";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '0';
+    rst <= '1';
+    din <= x"b4";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '1';
+    rst <= '1';
+    din <= x"b5";
+    pulse;
+    assert dout = x"00" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/tb_dff08b.vhdl b/testsuite/synth/dff02/tb_dff08b.vhdl
new file mode 100644
index 000000000..f01b6ecf1
--- /dev/null
+++ b/testsuite/synth/dff02/tb_dff08b.vhdl
@@ -0,0 +1,67 @@
+entity tb_dff08b is
+end tb_dff08b;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff08b is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal en : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff08b
+    port map (
+      q => dout,
+      d => din,
+      en => en,
+      clk => clk,
+      rst => rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    wait for 1 ns;
+    assert dout = x"aa" severity failure;
+
+    rst <= '1';
+    en <= '1';
+    pulse;
+    assert dout = x"00" severity failure;
+
+    rst <= '0';
+    din <= x"38";
+    pulse;
+    assert dout = x"38" severity failure;
+
+    din <= x"af";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '0';
+    din <= x"b3";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '0';
+    rst <= '1';
+    din <= x"b4";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '1';
+    rst <= '1';
+    din <= x"b5";
+    pulse;
+    assert dout = x"00" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/tb_dff08c.vhdl b/testsuite/synth/dff02/tb_dff08c.vhdl
new file mode 100644
index 000000000..12b4f6a3f
--- /dev/null
+++ b/testsuite/synth/dff02/tb_dff08c.vhdl
@@ -0,0 +1,67 @@
+entity tb_dff08c is
+end tb_dff08c;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff08c is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal en : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff08c
+    port map (
+      q => dout,
+      d => din,
+      en => en,
+      clk => clk,
+      rst => rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    wait for 1 ns;
+    assert dout = x"aa" severity failure;
+
+    rst <= '1';
+    en <= '1';
+    pulse;
+    assert dout = x"aa" severity failure;
+
+    rst <= '0';
+    din <= x"38";
+    pulse;
+    assert dout = x"38" severity failure;
+
+    din <= x"af";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '0';
+    din <= x"b3";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '0';
+    rst <= '1';
+    din <= x"b4";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '1';
+    rst <= '1';
+    din <= x"b5";
+    pulse;
+    assert dout = x"aa" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/tb_dff08d.vhdl b/testsuite/synth/dff02/tb_dff08d.vhdl
new file mode 100644
index 000000000..b096a8de2
--- /dev/null
+++ b/testsuite/synth/dff02/tb_dff08d.vhdl
@@ -0,0 +1,55 @@
+entity tb_dff08d is
+end tb_dff08d;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff08d is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal en : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff08d
+    port map (
+      q => dout,
+      d => din,
+      en => en,
+      clk => clk,
+      rst => rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    wait for 1 ns;
+    assert dout = x"aa" severity failure;
+
+    rst <= '1';
+    pulse;
+    assert dout = x"aa" severity failure;
+
+    rst <= '0';
+    din <= x"38";
+    pulse;
+    assert dout = x"38" severity failure;
+
+    din <= x"af";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '1';
+    rst <= '1';
+    din <= x"b5";
+    pulse;
+    assert dout = x"aa" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/testsuite.sh b/testsuite/synth/dff02/testsuite.sh
index aa13c2c90..e85d78d97 100755
--- a/testsuite/synth/dff02/testsuite.sh
+++ b/testsuite/synth/dff02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in dff05 dff06 dff08 dff09; do
+for t in dff05 dff06 dff08 dff08a dff08b dff08c dff08d dff09; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
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