From 8a35846d7e91f26d22cb059cfbf21d9e5645314d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 22 Mar 2020 08:24:54 +0100
Subject: testsuite/synth: add tests for previous commit.

---
 testsuite/synth/dff01/dff14.vhdl     | 20 ++++++++++++++++++
 testsuite/synth/dff01/dff15.vhdl     | 20 ++++++++++++++++++
 testsuite/synth/dff01/tb_dff14.vhdl  | 40 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/dff01/tb_dff15.vhdl  | 40 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/dff01/testsuite.sh   | 11 ++--------
 testsuite/synth/synth93/a.vhdl       | 28 +++++++++++++++++++++++++
 testsuite/synth/synth93/testsuite.sh |  8 ++++++++
 7 files changed, 158 insertions(+), 9 deletions(-)
 create mode 100644 testsuite/synth/dff01/dff14.vhdl
 create mode 100644 testsuite/synth/dff01/dff15.vhdl
 create mode 100644 testsuite/synth/dff01/tb_dff14.vhdl
 create mode 100644 testsuite/synth/dff01/tb_dff15.vhdl
 create mode 100644 testsuite/synth/synth93/a.vhdl
 create mode 100755 testsuite/synth/synth93/testsuite.sh

diff --git a/testsuite/synth/dff01/dff14.vhdl b/testsuite/synth/dff01/dff14.vhdl
new file mode 100644
index 000000000..daab02246
--- /dev/null
+++ b/testsuite/synth/dff01/dff14.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff14 is
+  port (q : out std_logic;
+        d : std_logic;
+        clk : std_logic);
+end dff14;
+
+architecture behav of dff14 is
+begin
+  process (clk) is
+    variable m : std_logic;
+  begin
+    if rising_edge (clk) then
+      m := d;
+    end if;
+    q <= m;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/dff15.vhdl b/testsuite/synth/dff01/dff15.vhdl
new file mode 100644
index 000000000..258c263c1
--- /dev/null
+++ b/testsuite/synth/dff01/dff15.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff15 is
+  port (q : out std_logic;
+        d : std_logic;
+        clk : std_logic);
+end dff15;
+
+architecture behav of dff15 is
+begin
+  process (clk) is
+    variable m : std_logic;
+  begin
+    if rising_edge (clk) then
+      m := d;
+    end if;
+    q <= not m;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff14.vhdl b/testsuite/synth/dff01/tb_dff14.vhdl
new file mode 100644
index 000000000..61d17dfc5
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff14.vhdl
@@ -0,0 +1,40 @@
+entity tb_dff14 is
+end tb_dff14;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff14 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.dff14
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff15.vhdl b/testsuite/synth/dff01/tb_dff15.vhdl
new file mode 100644
index 000000000..c8c82cdd1
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff15.vhdl
@@ -0,0 +1,40 @@
+entity tb_dff15 is
+end tb_dff15;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff15 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.dff15
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '1' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/testsuite.sh b/testsuite/synth/dff01/testsuite.sh
index d77be3b3d..d3352c4e0 100755
--- a/testsuite/synth/dff01/testsuite.sh
+++ b/testsuite/synth/dff01/testsuite.sh
@@ -3,15 +3,8 @@
 . ../../testenv.sh
 
 for t in dff01 dff02 dff03 dff04 dff05 dff06 dff07 dff08 dff09 \
-         dff10 dff11 dff12 dff13; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
+               dff10 dff11 dff12 dff13 dff14 dff15; do
+    synth_tb $t
 done
 
 echo "Test successful"
diff --git a/testsuite/synth/synth93/a.vhdl b/testsuite/synth/synth93/a.vhdl
new file mode 100644
index 000000000..0b2b5b6b2
--- /dev/null
+++ b/testsuite/synth/synth93/a.vhdl
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+
+entity A is
+  port (
+    clk : in std_logic;
+        input : in std_logic;
+        output : out std_logic
+    );
+
+end entity A;
+
+
+architecture RTL of A is
+begin
+
+    not_proc : process (clk)
+
+        variable not_input : std_logic := '0';
+
+    begin
+        if rising_edge(clk) then
+      not_input := not input;
+    end if;
+
+    output <= not_input;
+    end process;
+end RTL;
diff --git a/testsuite/synth/synth93/testsuite.sh b/testsuite/synth/synth93/testsuite.sh
new file mode 100755
index 000000000..f5bc3653e
--- /dev/null
+++ b/testsuite/synth/synth93/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze a
+clean
+
+echo "Test successful"
-- 
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