From 89c685deca6ba27f85332afef7f08b62fb029a58 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 4 Nov 2019 18:53:33 +0100 Subject: testsuite/synth: add a test for previous commit. --- testsuite/synth/aggr03/conv01.vhdl | 17 +++++++++++++++++ testsuite/synth/aggr03/tb_conv01.vhdl | 22 ++++++++++++++++++++++ testsuite/synth/aggr03/testsuite.sh | 17 +++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 testsuite/synth/aggr03/conv01.vhdl create mode 100644 testsuite/synth/aggr03/tb_conv01.vhdl create mode 100644 testsuite/synth/aggr03/testsuite.sh diff --git a/testsuite/synth/aggr03/conv01.vhdl b/testsuite/synth/aggr03/conv01.vhdl new file mode 100644 index 000000000..07ffa2835 --- /dev/null +++ b/testsuite/synth/aggr03/conv01.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity conv01 is + port (i : std_logic_vector (19 downto 0); + o : out std_logic_vector (31 downto 0)); +end conv01; + +architecture behav of conv01 is +begin + process (i) + variable v : std_logic_vector (31 downto 0); + begin + v := (i'left downto 0 => i, others => '0'); + o <= v; + end process; +end behav; diff --git a/testsuite/synth/aggr03/tb_conv01.vhdl b/testsuite/synth/aggr03/tb_conv01.vhdl new file mode 100644 index 000000000..32ea74d84 --- /dev/null +++ b/testsuite/synth/aggr03/tb_conv01.vhdl @@ -0,0 +1,22 @@ +entity tb_conv01 is +end tb_conv01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_conv01 is + signal i : std_logic_vector(19 downto 0); + signal o : std_logic_vector(31 downto 0); +begin + dut: entity work.conv01 + port map (i => i, o => o); + + process + begin + i <= x"abcde"; + wait for 1 ns; + assert o = x"000_abcde" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/aggr03/testsuite.sh b/testsuite/synth/aggr03/testsuite.sh new file mode 100644 index 000000000..effc23552 --- /dev/null +++ b/testsuite/synth/aggr03/testsuite.sh @@ -0,0 +1,17 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +for t in conv01; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean +done + +echo "Test successful" -- cgit v1.2.3