From 84516bdbe86290f475ad177371975991d38d065c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 23 May 2022 06:45:07 +0200
Subject: testsuite/synth: add a comments

---
 testsuite/synth/arr01/tb_arr04.vhdl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/testsuite/synth/arr01/tb_arr04.vhdl b/testsuite/synth/arr01/tb_arr04.vhdl
index 51801b258..63e01fa85 100644
--- a/testsuite/synth/arr01/tb_arr04.vhdl
+++ b/testsuite/synth/arr01/tb_arr04.vhdl
@@ -21,6 +21,8 @@ begin
     constant sov : std_logic_vector := b"0101";
     constant v_v : std_logic_vector := b"0011";
     constant r_v : std_logic_vector := b"0001";
+    --  reg0                             0001
+    --  reg1                             0011
   begin
     clk <= '0';
     rst <= '1';
-- 
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