From 82e970042ce5133df5de05410d7d0d5a43ace90b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 9 Mar 2023 18:44:08 +0100
Subject: testsuite/synth: add a test for selected signal assignment

---
 testsuite/synth/case01/case07.vhdl  | 17 +++++++++++++++++
 testsuite/synth/case01/testsuite.sh |  5 +++--
 2 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 testsuite/synth/case01/case07.vhdl

diff --git a/testsuite/synth/case01/case07.vhdl b/testsuite/synth/case01/case07.vhdl
new file mode 100644
index 000000000..deecf1e75
--- /dev/null
+++ b/testsuite/synth/case01/case07.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity case07 is
+  port (a : std_logic_vector (4 downto 0);
+        o : out std_logic);
+end case07;
+
+architecture behav of case07 is
+begin
+  process (a)
+  begin
+    with a select o <=
+      '1' when "00000",
+      '0' when others;
+  end process;
+end behav;
diff --git a/testsuite/synth/case01/testsuite.sh b/testsuite/synth/case01/testsuite.sh
index ef530ebe1..673d3beec 100755
--- a/testsuite/synth/case01/testsuite.sh
+++ b/testsuite/synth/case01/testsuite.sh
@@ -6,7 +6,8 @@ for t in case01 case02 case03 case04; do
     synth_tb $t
 done
 
-synth case05.vhdl -e case05 > syn_case05.vhdl
-synth case06.vhdl -e case06 > syn_case06.vhdl
+for t in case05 case06 case07; do
+  synth_only $t
+done
 
 echo "Test successful"
-- 
cgit v1.2.3