From 819514b98f5567830cfd3556d2042a3e4b974f4e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 3 Nov 2019 17:57:59 +0100
Subject: testsuite/synth: add a test for ram/rom.

---
 testsuite/synth/ram01/sram01.vhdl    | 29 ++++++++++++++++++++++++
 testsuite/synth/ram01/srom01.vhdl    | 28 +++++++++++++++++++++++
 testsuite/synth/ram01/tb_sram01.vhdl | 43 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/ram01/tb_srom01.vhdl | 38 +++++++++++++++++++++++++++++++
 testsuite/synth/ram01/testsuite.sh   | 16 ++++++++++++++
 5 files changed, 154 insertions(+)
 create mode 100644 testsuite/synth/ram01/sram01.vhdl
 create mode 100644 testsuite/synth/ram01/srom01.vhdl
 create mode 100644 testsuite/synth/ram01/tb_sram01.vhdl
 create mode 100644 testsuite/synth/ram01/tb_srom01.vhdl
 create mode 100755 testsuite/synth/ram01/testsuite.sh

diff --git a/testsuite/synth/ram01/sram01.vhdl b/testsuite/synth/ram01/sram01.vhdl
new file mode 100644
index 000000000..b4bfd0d2e
--- /dev/null
+++ b/testsuite/synth/ram01/sram01.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sram01 is
+  port (
+    clk_i  : std_logic;
+    addr_i : std_logic_vector(3 downto 0);
+    data_i : std_logic_vector(7 downto 0);
+    data_o : out std_logic_vector(7 downto 0);
+    wen_i   : std_logic);
+end sram01;
+
+architecture behav of sram01 is
+begin
+  process (clk_i, addr_i)
+    type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
+    variable mem : mem_type;
+    variable addr : natural range mem_type'range;
+  begin
+    if rising_edge(clk_i) then
+      addr := to_integer (unsigned (addr_i));
+      data_o <= mem (addr);
+      if wen_i = '1' then
+        mem (addr) := data_i;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/ram01/srom01.vhdl b/testsuite/synth/ram01/srom01.vhdl
new file mode 100644
index 000000000..1d8e70b64
--- /dev/null
+++ b/testsuite/synth/ram01/srom01.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity srom01 is
+  port (
+    clk_i  : std_logic;
+    addr_i : std_logic_vector(3 downto 0);
+    data_o : out std_logic_vector(7 downto 0));
+end srom01;
+
+architecture behav of srom01 is
+begin
+  process (clk_i, addr_i)
+    type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
+    constant mem : mem_type := (
+      x"f0", x"e1", x"d2", x"c3",
+      x"b4", x"a5", x"96", x"87",
+      x"78", x"69", x"5a", x"4b",
+      x"3c", x"2d", x"1e", x"0f");
+    variable addr : natural range mem_type'range;
+  begin
+    if rising_edge(clk_i) then
+      addr := to_integer (unsigned (addr_i));
+      data_o <= mem (addr);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/ram01/tb_sram01.vhdl b/testsuite/synth/ram01/tb_sram01.vhdl
new file mode 100644
index 000000000..6fa0a7106
--- /dev/null
+++ b/testsuite/synth/ram01/tb_sram01.vhdl
@@ -0,0 +1,43 @@
+entity tb_sram01 is
+end tb_sram01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sram01 is
+  signal addr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal wen : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.sram01
+    port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat,
+              wen_i => wen);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    addr <= "0000";
+    wdat <= x"01";
+    wen <= '1';
+    pulse;
+
+    addr <= "0001";
+    wdat <= x"02";
+    pulse;
+
+    addr <= "0000";
+    wen <= '0';
+    pulse;
+    assert rdat = x"01" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/ram01/tb_srom01.vhdl b/testsuite/synth/ram01/tb_srom01.vhdl
new file mode 100644
index 000000000..530423a67
--- /dev/null
+++ b/testsuite/synth/ram01/tb_srom01.vhdl
@@ -0,0 +1,38 @@
+entity tb_srom01 is
+end tb_srom01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_srom01 is
+  signal addr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.srom01
+    port map (clk_i => clk, addr_i => addr, data_o => rdat);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    addr <= "0000";
+    pulse;
+    assert rdat = x"f0" severity failure;
+
+    addr <= "0001";
+    pulse;
+    assert rdat = x"e1" severity failure;
+
+    addr <= "0100";
+    pulse;
+    assert rdat = x"b4" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/ram01/testsuite.sh b/testsuite/synth/ram01/testsuite.sh
new file mode 100755
index 000000000..6254b1ab6
--- /dev/null
+++ b/testsuite/synth/ram01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in sram01 srom01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"
-- 
cgit v1.2.3