From 7bafc11a48a61526093ce2ce31fc5d91bd1a4a0f Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 20 Jul 2019 18:52:06 +0200
Subject: synth: fix test name.

---
 testsuite/synth/forgen01.vhdl/forgen01.vhdl    | 14 --------------
 testsuite/synth/forgen01.vhdl/tb_forgen01.vhdl | 19 -------------------
 testsuite/synth/forgen01.vhdl/testsuite.sh     | 16 ----------------
 testsuite/synth/forgen01/forgen01.vhdl         | 14 ++++++++++++++
 testsuite/synth/forgen01/tb_forgen01.vhdl      | 19 +++++++++++++++++++
 testsuite/synth/forgen01/testsuite.sh          | 16 ++++++++++++++++
 6 files changed, 49 insertions(+), 49 deletions(-)
 delete mode 100644 testsuite/synth/forgen01.vhdl/forgen01.vhdl
 delete mode 100644 testsuite/synth/forgen01.vhdl/tb_forgen01.vhdl
 delete mode 100755 testsuite/synth/forgen01.vhdl/testsuite.sh
 create mode 100644 testsuite/synth/forgen01/forgen01.vhdl
 create mode 100644 testsuite/synth/forgen01/tb_forgen01.vhdl
 create mode 100755 testsuite/synth/forgen01/testsuite.sh

diff --git a/testsuite/synth/forgen01.vhdl/forgen01.vhdl b/testsuite/synth/forgen01.vhdl/forgen01.vhdl
deleted file mode 100644
index b3e5a0eb0..000000000
--- a/testsuite/synth/forgen01.vhdl/forgen01.vhdl
+++ /dev/null
@@ -1,14 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity forgen01 is
-  port (a : out std_logic_vector (7 downto 0));
-end;
-
-architecture behav of forgen01 is
-  constant c : std_logic_vector (7 downto 0) := x"a1";
-begin
-  gen: for i in a'range generate
-    a (i) <= c (i);
-  end generate;
-end behav;
diff --git a/testsuite/synth/forgen01.vhdl/tb_forgen01.vhdl b/testsuite/synth/forgen01.vhdl/tb_forgen01.vhdl
deleted file mode 100644
index df0698fcc..000000000
--- a/testsuite/synth/forgen01.vhdl/tb_forgen01.vhdl
+++ /dev/null
@@ -1,19 +0,0 @@
-entity tb_forgen01 is
-end tb_forgen01;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-architecture behav of tb_forgen01 is
-  signal a : std_logic_vector (7 downto 0);
-begin
-  dut: entity work.forgen01
-    port map (a);
-
-  process
-  begin
-    wait for 1 ns;
-    assert a = x"a1" severity failure;
-    wait;
-  end process;
-end behav;
diff --git a/testsuite/synth/forgen01.vhdl/testsuite.sh b/testsuite/synth/forgen01.vhdl/testsuite.sh
deleted file mode 100755
index 70ee6bc2a..000000000
--- a/testsuite/synth/forgen01.vhdl/testsuite.sh
+++ /dev/null
@@ -1,16 +0,0 @@
-#! /bin/sh
-
-. ../../testenv.sh
-
-for t in forgen01; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-done
-
-echo "Test successful"
diff --git a/testsuite/synth/forgen01/forgen01.vhdl b/testsuite/synth/forgen01/forgen01.vhdl
new file mode 100644
index 000000000..b3e5a0eb0
--- /dev/null
+++ b/testsuite/synth/forgen01/forgen01.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity forgen01 is
+  port (a : out std_logic_vector (7 downto 0));
+end;
+
+architecture behav of forgen01 is
+  constant c : std_logic_vector (7 downto 0) := x"a1";
+begin
+  gen: for i in a'range generate
+    a (i) <= c (i);
+  end generate;
+end behav;
diff --git a/testsuite/synth/forgen01/tb_forgen01.vhdl b/testsuite/synth/forgen01/tb_forgen01.vhdl
new file mode 100644
index 000000000..df0698fcc
--- /dev/null
+++ b/testsuite/synth/forgen01/tb_forgen01.vhdl
@@ -0,0 +1,19 @@
+entity tb_forgen01 is
+end tb_forgen01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_forgen01 is
+  signal a : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.forgen01
+    port map (a);
+
+  process
+  begin
+    wait for 1 ns;
+    assert a = x"a1" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/forgen01/testsuite.sh b/testsuite/synth/forgen01/testsuite.sh
new file mode 100755
index 000000000..70ee6bc2a
--- /dev/null
+++ b/testsuite/synth/forgen01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in forgen01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"
-- 
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