From 7a6ab8c14858a09b87be025e267eff5192e99c08 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 19 Mar 2020 08:56:05 +0100
Subject: testsuite/synth: add a test for #1161

---
 testsuite/synth/issue1161/issue1.vhdl    | 11 +++++++++++
 testsuite/synth/issue1161/issue2.vhdl    | 11 +++++++++++
 testsuite/synth/issue1161/issue3.vhdl    | 11 +++++++++++
 testsuite/synth/issue1161/tb_issue1.vhdl | 19 +++++++++++++++++++
 testsuite/synth/issue1161/tb_issue2.vhdl | 19 +++++++++++++++++++
 testsuite/synth/issue1161/tb_issue3.vhdl | 18 ++++++++++++++++++
 testsuite/synth/issue1161/testsuite.sh   | 15 +++++++++++++++
 7 files changed, 104 insertions(+)
 create mode 100644 testsuite/synth/issue1161/issue1.vhdl
 create mode 100644 testsuite/synth/issue1161/issue2.vhdl
 create mode 100644 testsuite/synth/issue1161/issue3.vhdl
 create mode 100644 testsuite/synth/issue1161/tb_issue1.vhdl
 create mode 100644 testsuite/synth/issue1161/tb_issue2.vhdl
 create mode 100644 testsuite/synth/issue1161/tb_issue3.vhdl
 create mode 100755 testsuite/synth/issue1161/testsuite.sh

diff --git a/testsuite/synth/issue1161/issue1.vhdl b/testsuite/synth/issue1161/issue1.vhdl
new file mode 100644
index 000000000..db1ed6aa1
--- /dev/null
+++ b/testsuite/synth/issue1161/issue1.vhdl
@@ -0,0 +1,11 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue1 is
+   port (foo : out std_logic_vector(4-1 downto 0));
+end issue1;
+
+architecture rtl of issue1 is
+begin
+    foo <= ("0",others=>'1');
+end architecture;
diff --git a/testsuite/synth/issue1161/issue2.vhdl b/testsuite/synth/issue1161/issue2.vhdl
new file mode 100644
index 000000000..fdfb7477a
--- /dev/null
+++ b/testsuite/synth/issue1161/issue2.vhdl
@@ -0,0 +1,11 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue2 is
+   port (foo : out std_logic_vector(4-1 downto 0));
+end issue2;
+
+architecture rtl of issue2 is
+begin
+    foo <= (2 downto 1 => "00" ,others=>'1');
+end architecture;
diff --git a/testsuite/synth/issue1161/issue3.vhdl b/testsuite/synth/issue1161/issue3.vhdl
new file mode 100644
index 000000000..d993d1055
--- /dev/null
+++ b/testsuite/synth/issue1161/issue3.vhdl
@@ -0,0 +1,11 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue3 is
+   port (foo : out std_logic_vector(4-1 downto 0));
+end issue3;
+
+architecture rtl of issue3 is
+begin
+    foo <= ("01", "10");
+end architecture;
diff --git a/testsuite/synth/issue1161/tb_issue1.vhdl b/testsuite/synth/issue1161/tb_issue1.vhdl
new file mode 100644
index 000000000..c8f601fcc
--- /dev/null
+++ b/testsuite/synth/issue1161/tb_issue1.vhdl
@@ -0,0 +1,19 @@
+entity tb_issue1 is
+end tb_issue1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_issue1 is
+  signal a : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.issue1
+    port map (a);
+
+  process
+  begin
+    wait for 1 ns;
+    assert a = "0111" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1161/tb_issue2.vhdl b/testsuite/synth/issue1161/tb_issue2.vhdl
new file mode 100644
index 000000000..b853f7ee4
--- /dev/null
+++ b/testsuite/synth/issue1161/tb_issue2.vhdl
@@ -0,0 +1,19 @@
+entity tb_issue2 is
+end tb_issue2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_issue2 is
+  signal a : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.issue2
+    port map (a);
+
+  process
+  begin
+    wait for 1 ns;
+    assert a = "1001" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1161/tb_issue3.vhdl b/testsuite/synth/issue1161/tb_issue3.vhdl
new file mode 100644
index 000000000..c37a41e3b
--- /dev/null
+++ b/testsuite/synth/issue1161/tb_issue3.vhdl
@@ -0,0 +1,18 @@
+entity tb_issue3 is
+end tb_issue3;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_issue3 is
+  signal a : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.issue3
+    port map (a);
+
+  process
+  begin
+    assert a = "0110" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1161/testsuite.sh b/testsuite/synth/issue1161/testsuite.sh
new file mode 100755
index 000000000..b01db04b4
--- /dev/null
+++ b/testsuite/synth/issue1161/testsuite.sh
@@ -0,0 +1,15 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in issue1 issue2; do
+    synth_tb $t
+done
+
+# TODO: simulation fails
+synth_analyze issue3
+
+clean
+
+echo "Test successful"
-- 
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