From 79c615e88dd652d7f2077ccdbef0487d74febd98 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 3 Nov 2019 07:38:22 +0100 Subject: synth: cap max in synth_slice_suffix --- src/synth/synth-expr.adb | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 628f1d589..02700859f 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -1209,6 +1209,7 @@ package body Synth.Expr is Dir : Iir_Direction; Step : Uns32; Max : Uns32; + Inp_W : Width; begin Off := 0; @@ -1260,16 +1261,22 @@ package body Synth.Expr is Synth_Extract_Dyn_Suffix (Name, Pfx_Bnd, Get_Net (Left), Get_Net (Right), Inp, Step, Off, Wd); + Inp_W := Get_Width (Inp); -- FIXME: convert range to offset. + -- Extract max from the range. -- example: len=128 wd=8 step=8 => max=16 -- len=8 wd=4 step=1 => max=4 -- max so that max*step+wd <= len - off -- max <= (len - off - wd) / step Max := (Pfx_Bnd.Len - Off - Wd) / Step; + if Clog2 (Uns64 (Max)) > Natural (Inp_W) then + -- The width of Inp limits the max. + Max := 2**Natural (Inp_W) - 1; + end if; Inp := Build_Memidx (Get_Build (Syn_Inst), Inp, Step * El_Wd, Max, - Get_Width (Inp) + Width (Clog2 (Uns64 (Step * El_Wd)))); + Inp_W + Width (Clog2 (Uns64 (Step * El_Wd)))); Wd := Wd * El_Wd; end if; end Synth_Slice_Suffix; -- cgit v1.2.3