From 73b75b927177d2d6553e6b86e325537a38f39527 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 1 Jan 2021 18:05:53 +0100
Subject: testsuite/synth: add a test for #1563

---
 testsuite/synth/issue1563/bug.vhdl     | 22 ++++++++++++++++++++++
 testsuite/synth/issue1563/bug2.vhdl    | 22 ++++++++++++++++++++++
 testsuite/synth/issue1563/bug3.vhdl    | 23 +++++++++++++++++++++++
 testsuite/synth/issue1563/bug4.vhdl    | 25 +++++++++++++++++++++++++
 testsuite/synth/issue1563/tb_bug.vhdl  | 24 ++++++++++++++++++++++++
 testsuite/synth/issue1563/tb_bug2.vhdl | 24 ++++++++++++++++++++++++
 testsuite/synth/issue1563/tb_bug4.vhdl | 24 ++++++++++++++++++++++++
 testsuite/synth/issue1563/testsuite.sh |  9 +++++++++
 8 files changed, 173 insertions(+)
 create mode 100644 testsuite/synth/issue1563/bug.vhdl
 create mode 100644 testsuite/synth/issue1563/bug2.vhdl
 create mode 100644 testsuite/synth/issue1563/bug3.vhdl
 create mode 100644 testsuite/synth/issue1563/bug4.vhdl
 create mode 100644 testsuite/synth/issue1563/tb_bug.vhdl
 create mode 100644 testsuite/synth/issue1563/tb_bug2.vhdl
 create mode 100644 testsuite/synth/issue1563/tb_bug4.vhdl
 create mode 100755 testsuite/synth/issue1563/testsuite.sh

diff --git a/testsuite/synth/issue1563/bug.vhdl b/testsuite/synth/issue1563/bug.vhdl
new file mode 100644
index 000000000..1f75b7353
--- /dev/null
+++ b/testsuite/synth/issue1563/bug.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity bug is
+port (
+    clock : in std_logic;
+    output : out std_logic
+);
+end bug;
+
+architecture bug_arch OF bug is
+begin
+    process (clock)
+    begin
+        if rising_edge(clock) then
+            output <= '1';
+        end if;
+        if rising_edge(clock) then
+            output <= '0';
+        end if;
+    end process;
+end bug_arch;
diff --git a/testsuite/synth/issue1563/bug2.vhdl b/testsuite/synth/issue1563/bug2.vhdl
new file mode 100644
index 000000000..bb180029c
--- /dev/null
+++ b/testsuite/synth/issue1563/bug2.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity bug2 is
+port (
+    clock : in std_logic;
+    output : out std_logic_vector(3 downto 0)
+);
+end;
+
+architecture bug_arch OF bug2 is
+begin
+    process (clock)
+    begin
+        if rising_edge(clock) then
+            output <= "0010";
+        end if;
+        if rising_edge(clock) then
+            output(2) <= '1';
+        end if;
+    end process;
+end bug_arch;
diff --git a/testsuite/synth/issue1563/bug3.vhdl b/testsuite/synth/issue1563/bug3.vhdl
new file mode 100644
index 000000000..10da2bd17
--- /dev/null
+++ b/testsuite/synth/issue1563/bug3.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity bug3 is
+port (
+  clock : in std_logic;
+  reset : std_logic;
+  input : std_logic_vector(3 downto 0);
+  output : out std_logic_vector(3 downto 0)
+);
+end;
+
+architecture bug_arch OF bug3 is
+begin
+    process (clock)
+    begin
+      if reset = '1' then
+        output(0) <= '0';
+      elsif rising_edge(clock) then
+        output <= input;
+      end if;
+    end process;
+end bug_arch;
diff --git a/testsuite/synth/issue1563/bug4.vhdl b/testsuite/synth/issue1563/bug4.vhdl
new file mode 100644
index 000000000..2973e5798
--- /dev/null
+++ b/testsuite/synth/issue1563/bug4.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity bug4 is
+port (
+    clock : in std_logic;
+    output : out std_logic
+);
+end;
+
+architecture bug_arch OF bug4 is
+  signal t : std_logic := '1';
+begin
+    process (clock)
+    begin
+        if rising_edge(clock) then
+            t <= '1';
+        end if;
+        if rising_edge(clock) then
+            t <= '0';
+        end if;
+    end process;
+
+    output <= t;
+end bug_arch;
diff --git a/testsuite/synth/issue1563/tb_bug.vhdl b/testsuite/synth/issue1563/tb_bug.vhdl
new file mode 100644
index 000000000..62b58983d
--- /dev/null
+++ b/testsuite/synth/issue1563/tb_bug.vhdl
@@ -0,0 +1,24 @@
+entity tb_bug is
+end tb_bug;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_bug is
+  signal clk : std_logic;
+  signal o : std_logic;
+begin
+  dut: entity work.bug
+    port map (clk, o);
+
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    assert o = 'U' severity failure;
+    clk <= '1';
+    wait for 1 ns;
+    assert o = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1563/tb_bug2.vhdl b/testsuite/synth/issue1563/tb_bug2.vhdl
new file mode 100644
index 000000000..b72909a59
--- /dev/null
+++ b/testsuite/synth/issue1563/tb_bug2.vhdl
@@ -0,0 +1,24 @@
+entity tb_bug2 is
+end tb_bug2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_bug2 is
+  signal clk : std_logic;
+  signal o : std_logic_vector(3 downto 0);
+begin
+  dut: entity work.bug2
+    port map (clk, o);
+
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    assert o = "UUUU" severity failure;
+    clk <= '1';
+    wait for 1 ns;
+    assert o = "0110" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1563/tb_bug4.vhdl b/testsuite/synth/issue1563/tb_bug4.vhdl
new file mode 100644
index 000000000..9df012ee3
--- /dev/null
+++ b/testsuite/synth/issue1563/tb_bug4.vhdl
@@ -0,0 +1,24 @@
+entity tb_bug4 is
+end tb_bug4;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_bug4 is
+  signal clk : std_logic;
+  signal o : std_logic;
+begin
+  dut: entity work.bug4
+    port map (clk, o);
+
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    assert o = '1' severity failure;
+    clk <= '1';
+    wait for 1 ns;
+    assert o = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1563/testsuite.sh b/testsuite/synth/issue1563/testsuite.sh
new file mode 100755
index 000000000..df797b117
--- /dev/null
+++ b/testsuite/synth/issue1563/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in bug bug4 bug2; do
+    synth_tb $t
+done
+
+echo "Test successful"
-- 
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