From 5fbe7eadaeb56ca29553c0cf6564a2151da5b423 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 2 Jan 2023 19:40:11 +0100
Subject: simul: skip psl default clock in declarations

---
 src/simul/simul-vhdl_elab.adb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index fed1c7d74..229c75c77 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -439,6 +439,7 @@ package body Simul.Vhdl_Elab is
            | Iir_Kind_Component_Declaration
            | Iir_Kind_File_Declaration
            | Iir_Kind_Protected_Type_Body
+           | Iir_Kind_Psl_Default_Clock
            | Iir_Kind_Use_Clause
            | Iir_Kind_Group_Template_Declaration
            | Iir_Kind_Group_Declaration =>
-- 
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