From 5b80233e0715b352df14c2833e400bff429bdbdf Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 17 Feb 2022 07:50:31 +0100
Subject: testsuite/synth: add a test for #1972

---
 testsuite/synth/issue1972/ent.vhdl     | 12 ++++++++++++
 testsuite/synth/issue1972/testsuite.sh |  7 +++++++
 2 files changed, 19 insertions(+)
 create mode 100644 testsuite/synth/issue1972/ent.vhdl
 create mode 100755 testsuite/synth/issue1972/testsuite.sh

diff --git a/testsuite/synth/issue1972/ent.vhdl b/testsuite/synth/issue1972/ent.vhdl
new file mode 100644
index 000000000..502f47785
--- /dev/null
+++ b/testsuite/synth/issue1972/ent.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+  port (output : out std_ulogic);
+end entity;
+
+architecture rtl of ent is
+  signal sr : std_ulogic_vector(0 downto 1);
+begin
+  output <= sr(1);
+end architecture;
diff --git a/testsuite/synth/issue1972/testsuite.sh b/testsuite/synth/issue1972/testsuite.sh
new file mode 100755
index 000000000..f6f8ea08f
--- /dev/null
+++ b/testsuite/synth/issue1972/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_failure ent.vhdl -e
+
+echo "Test successful"
-- 
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