From 5a846b7a38cf74f2969706dfeadad61f6bebf9e1 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 30 Jul 2019 20:57:32 +0200
Subject: synth: add dpram3 test.

---
 testsuite/synth/arr02/dpram3.vhdl    | 24 +++++++++++++++++
 testsuite/synth/arr02/tb_dpram3.vhdl | 52 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/arr02/testsuite.sh   |  2 +-
 3 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/arr02/dpram3.vhdl
 create mode 100644 testsuite/synth/arr02/tb_dpram3.vhdl

diff --git a/testsuite/synth/arr02/dpram3.vhdl b/testsuite/synth/arr02/dpram3.vhdl
new file mode 100644
index 000000000..a04478809
--- /dev/null
+++ b/testsuite/synth/arr02/dpram3.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram3 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram3;
+
+architecture behav of dpram3 is
+begin
+  process (clk)
+    type memtype is array (0 to 15) of std_logic_vector (7 downto 0);
+    variable mem : memtype;
+  begin
+    if rising_edge (clk) then
+      rdat <= mem (to_integer(unsigned (raddr)));
+      mem (to_integer(unsigned (waddr))) := wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/tb_dpram3.vhdl b/testsuite/synth/arr02/tb_dpram3.vhdl
new file mode 100644
index 000000000..9cdbd8af7
--- /dev/null
+++ b/testsuite/synth/arr02/tb_dpram3.vhdl
@@ -0,0 +1,52 @@
+entity tb_dpram3 is
+end tb_dpram3;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram3 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram3
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    raddr <= "0000";
+    waddr <= x"a";
+    wdat <= x"5a";
+    pulse;
+
+    raddr <= x"a";
+    waddr <= x"7";
+    wdat <= x"87";
+    pulse;
+    assert rdat = x"5a" severity failure;
+
+    raddr <= x"7";
+    waddr <= x"1";
+    wdat <= x"e1";
+    pulse;
+    assert rdat = x"87" severity failure;
+
+    raddr <= x"1";
+    waddr <= x"3";
+    wdat <= x"c3";
+    pulse;
+    assert rdat = x"e1" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/testsuite.sh b/testsuite/synth/arr02/testsuite.sh
index 6dd2fb477..8d0b840a5 100755
--- a/testsuite/synth/arr02/testsuite.sh
+++ b/testsuite/synth/arr02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in rom1 dpram1 dpram2; do
+for t in rom1 dpram1 dpram2 dpram3; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
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