From 4bc06244b352f0145f9b47579702f2259cbdabfc Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 8 Oct 2019 06:34:50 +0200
Subject: testsuite/synth: add another test.

---
 testsuite/synth/dff02/dff08.vhdl    | 25 +++++++++++++++
 testsuite/synth/dff02/tb_dff08.vhdl | 64 +++++++++++++++++++++++++++++++++++++
 testsuite/synth/dff02/testsuite.sh  |  2 +-
 3 files changed, 90 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/dff02/dff08.vhdl
 create mode 100644 testsuite/synth/dff02/tb_dff08.vhdl

diff --git a/testsuite/synth/dff02/dff08.vhdl b/testsuite/synth/dff02/dff08.vhdl
new file mode 100644
index 000000000..da12d2075
--- /dev/null
+++ b/testsuite/synth/dff02/dff08.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff08 is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic;
+        en : std_logic;
+        rst : std_logic);
+end dff08;
+
+architecture behav of dff08 is
+  signal p : std_logic_vector(7 downto 0);
+begin
+  process (clk, rst) is
+  begin
+    if en = '0' then
+      null;
+    elsif rst = '1' then
+      q <= x"00";
+    elsif rising_edge (clk) then
+      q <= d;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/tb_dff08.vhdl b/testsuite/synth/dff02/tb_dff08.vhdl
new file mode 100644
index 000000000..671821c3c
--- /dev/null
+++ b/testsuite/synth/dff02/tb_dff08.vhdl
@@ -0,0 +1,64 @@
+entity tb_dff08 is
+end tb_dff08;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff08 is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal en : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff08
+    port map (
+      q => dout,
+      d => din,
+      en => en,
+      clk => clk,
+      rst => rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    en <= '1';
+    pulse;
+    assert dout = x"00" severity failure;
+
+    rst <= '0';
+    din <= x"38";
+    pulse;
+    assert dout = x"38" severity failure;
+
+    din <= x"af";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '0';
+    din <= x"b3";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '0';
+    rst <= '1';
+    din <= x"b4";
+    pulse;
+    assert dout = x"af" severity failure;
+
+    en <= '1';
+    rst <= '1';
+    din <= x"b5";
+    pulse;
+    assert dout = x"00" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/testsuite.sh b/testsuite/synth/dff02/testsuite.sh
index dae869ec7..46be7defd 100755
--- a/testsuite/synth/dff02/testsuite.sh
+++ b/testsuite/synth/dff02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in dff06; do
+for t in dff06 dff08; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
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