From 43f70120eb51d9d5ff8e429e0128d12b8c302fe2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 8 Sep 2019 16:30:32 +0200
Subject: testsuite/synth: add a test for slices.

---
 testsuite/synth/slice01/slice02.vhdl    | 28 ++++++++++++++++++++++++++++
 testsuite/synth/slice01/tb_slice02.vhdl | 33 +++++++++++++++++++++++++++++++++
 testsuite/synth/slice01/testsuite.sh    |  4 ++--
 3 files changed, 63 insertions(+), 2 deletions(-)
 create mode 100644 testsuite/synth/slice01/slice02.vhdl
 create mode 100644 testsuite/synth/slice01/tb_slice02.vhdl

diff --git a/testsuite/synth/slice01/slice02.vhdl b/testsuite/synth/slice01/slice02.vhdl
new file mode 100644
index 000000000..661c7aa16
--- /dev/null
+++ b/testsuite/synth/slice01/slice02.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity slice02 is
+  generic (w: natural := 4);
+  port (clk : std_logic;
+        dat : std_logic_vector (7 downto 0);
+        mask : std_logic_vector (1 downto 0);
+        res : out std_logic_vector (7 downto 0));
+end slice02;
+
+architecture behav of slice02 is
+begin
+  process(clk)
+    variable hi, lo : natural;
+  begin
+    if rising_edge (clk) then
+      res <= (others => '0');
+      for i in mask'range loop
+        if mask (i) = '1' then
+          lo := i * 4;
+          hi := lo + 3;
+          res (hi downto lo) <= dat (hi downto lo);
+        end if;
+      end loop;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/slice01/tb_slice02.vhdl b/testsuite/synth/slice01/tb_slice02.vhdl
new file mode 100644
index 000000000..7a377d244
--- /dev/null
+++ b/testsuite/synth/slice01/tb_slice02.vhdl
@@ -0,0 +1,33 @@
+entity tb_slice02 is
+end tb_slice02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_slice02 is
+  signal clk : std_logic;
+  signal di : std_logic_vector (7 downto 0);
+  signal mask : std_logic_vector (1 downto 0);
+  signal do : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.slice02
+    generic map (w => 4)
+    port map (clk, di, mask, do);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+    constant b0 : std_logic_vector (3 downto 0) := "1101";
+  begin
+    di <= x"12";
+    mask <= "11";
+    pulse;
+    assert do = x"12" severity error;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/slice01/testsuite.sh b/testsuite/synth/slice01/testsuite.sh
index 1729c688d..0220769ab 100755
--- a/testsuite/synth/slice01/testsuite.sh
+++ b/testsuite/synth/slice01/testsuite.sh
@@ -2,14 +2,14 @@
 
 . ../../testenv.sh
 
-for t in slice01; do
+for t in slice01 slice02; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
 
     synth $t.vhdl -e $t > syn_$t.vhdl
     analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
     clean
 done
 
-- 
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