From 4284956d63b11db7e6b003f9c5ca81ea6eb234ff Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 16 Feb 2020 21:26:31 +0100
Subject: testsuite/synth: add test for previous commit.

---
 testsuite/synth/cnt01/cnt04.vhdl    | 28 ++++++++++++++++++++++++++++
 testsuite/synth/cnt01/tb_cnt04.vhdl | 36 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/cnt01/testsuite.sh  |  2 +-
 3 files changed, 65 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/cnt01/cnt04.vhdl
 create mode 100644 testsuite/synth/cnt01/tb_cnt04.vhdl

diff --git a/testsuite/synth/cnt01/cnt04.vhdl b/testsuite/synth/cnt01/cnt04.vhdl
new file mode 100644
index 000000000..1836c7587
--- /dev/null
+++ b/testsuite/synth/cnt01/cnt04.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.ALL;
+
+entity cnt04 is
+  port (
+    clk       : in std_logic;
+    rst       : in std_logic;
+
+    counter : out std_logic_vector (7 downto 0)
+    );
+end cnt04;
+
+architecture behav of cnt04 is
+  signal s_count : unsigned(7 downto 0); -- := (others => '0');
+begin
+  process(clk, rst)
+  begin
+    if rst = '1' then
+      s_count <= (others => '0');
+    elsif rising_edge(clk) then
+      s_count <= s_count + 1;
+    end if;
+  end process;
+
+  -- connect internal signal to output
+  counter <= std_logic_vector(s_count + 1);
+end behav;
diff --git a/testsuite/synth/cnt01/tb_cnt04.vhdl b/testsuite/synth/cnt01/tb_cnt04.vhdl
new file mode 100644
index 000000000..184f941d1
--- /dev/null
+++ b/testsuite/synth/cnt01/tb_cnt04.vhdl
@@ -0,0 +1,36 @@
+entity tb_cnt04 is
+end tb_cnt04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_cnt04 is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal counter : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.cnt04
+    port map (clk => clk, rst => rst, counter => counter);
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    pulse;
+    assert counter = x"01" severity failure;
+
+    rst <= '0';
+    pulse;
+    assert counter = x"02" severity failure;
+
+    pulse;
+    assert counter = x"03" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/cnt01/testsuite.sh b/testsuite/synth/cnt01/testsuite.sh
index f01df2cc7..4e2d78326 100755
--- a/testsuite/synth/cnt01/testsuite.sh
+++ b/testsuite/synth/cnt01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in cnt01 cnt02; do
+for t in cnt01 cnt02 cnt04; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
cgit v1.2.3