From 415e571ee0b532ff2002f2b8a4f67dc7ce56e155 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 17 Nov 2017 20:18:26 +0100
Subject: Add testcase for #461

---
 testsuite/gna/issue461/repro1.vhdl  | 14 ++++++++++++++
 testsuite/gna/issue461/test.vhdl    | 18 ++++++++++++++++++
 testsuite/gna/issue461/testsuite.sh | 11 +++++++++++
 3 files changed, 43 insertions(+)
 create mode 100644 testsuite/gna/issue461/repro1.vhdl
 create mode 100644 testsuite/gna/issue461/test.vhdl
 create mode 100755 testsuite/gna/issue461/testsuite.sh

diff --git a/testsuite/gna/issue461/repro1.vhdl b/testsuite/gna/issue461/repro1.vhdl
new file mode 100644
index 000000000..20131f019
--- /dev/null
+++ b/testsuite/gna/issue461/repro1.vhdl
@@ -0,0 +1,14 @@
+entity repro is
+end repro;
+
+architecture behaviour of repro is
+    signal selector : bit_vector(1 downto 0) := "10";
+    signal result   : bit_vector(7 downto 0);
+
+    signal op_1     : bit_vector(7 downto 0);
+    signal op_2     : bit_vector(7 downto 0);
+begin
+    with selector select
+        result <= op_1 and op_2 when "00",
+                  (others => '0') when others;
+end behaviour;
diff --git a/testsuite/gna/issue461/test.vhdl b/testsuite/gna/issue461/test.vhdl
new file mode 100644
index 000000000..c88ba0ee7
--- /dev/null
+++ b/testsuite/gna/issue461/test.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+end test;
+
+architecture behaviour of test is
+    signal selector : std_logic_vector(1 downto 0) := "UU";
+    signal result   : std_logic_vector(7 downto 0);
+
+    signal op_1     : std_logic_vector(7 downto 0);
+    signal op_2     : std_logic_vector(7 downto 0);
+begin
+    with selector select
+        result <= (std_logic_vector(signed(op_1) + signed(op_2))) when "00",
+                  (others => '-') when others;
+end behaviour;
diff --git a/testsuite/gna/issue461/testsuite.sh b/testsuite/gna/issue461/testsuite.sh
new file mode 100755
index 000000000..1d84c0f57
--- /dev/null
+++ b/testsuite/gna/issue461/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"
-- 
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