From 3d81a74f66c2440ebde7efc64415d6c5510e94ee Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 22 Nov 2018 20:47:08 +0100
Subject: Add testcase for #473

---
 testsuite/gna/issue473/repro.vhdl   | 17 +++++++++++++++++
 testsuite/gna/issue473/repro2.vhdl  | 20 ++++++++++++++++++++
 testsuite/gna/issue473/tbmem.vhdl   | 27 +++++++++++++++++++++++++++
 testsuite/gna/issue473/testsuite.sh | 11 +++++++++++
 4 files changed, 75 insertions(+)
 create mode 100644 testsuite/gna/issue473/repro.vhdl
 create mode 100644 testsuite/gna/issue473/repro2.vhdl
 create mode 100644 testsuite/gna/issue473/tbmem.vhdl
 create mode 100755 testsuite/gna/issue473/testsuite.sh

diff --git a/testsuite/gna/issue473/repro.vhdl b/testsuite/gna/issue473/repro.vhdl
new file mode 100644
index 000000000..a4590b2a4
--- /dev/null
+++ b/testsuite/gna/issue473/repro.vhdl
@@ -0,0 +1,17 @@
+entity repro is
+end entity repro;
+
+architecture TB of repro is
+
+begin
+
+    DM: process
+        type t_ram is array(natural range <>) of bit_vector;
+        type p_ram is access t_ram;
+        variable myram : p_ram;
+    begin
+        myram := new t_ram(0 to 31)(15 downto 0);
+        wait;
+    end process DM;
+    
+end architecture TB;
diff --git a/testsuite/gna/issue473/repro2.vhdl b/testsuite/gna/issue473/repro2.vhdl
new file mode 100644
index 000000000..6ab9c4bbd
--- /dev/null
+++ b/testsuite/gna/issue473/repro2.vhdl
@@ -0,0 +1,20 @@
+entity repro is
+end entity repro;
+
+architecture TB of repro is
+
+begin
+
+    DM: process
+        type t_ram is array(natural range <>) of bit_vector;
+        type p_ram is access t_ram;
+        variable myram : p_ram;
+    begin
+        myram := new t_ram(0 to 31)(15 downto 0);
+        for i in myram'range loop
+            myram(i) := (others => '0');
+        end loop;
+        wait;
+    end process DM;
+    
+end architecture TB;
diff --git a/testsuite/gna/issue473/tbmem.vhdl b/testsuite/gna/issue473/tbmem.vhdl
new file mode 100644
index 000000000..a31a29520
--- /dev/null
+++ b/testsuite/gna/issue473/tbmem.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tbmem is
+end entity tbmem;
+
+architecture TB of tbmem is
+
+begin
+
+    DM: process
+        type t_ram is array(natural range <>) of unsigned;
+        type p_ram is access t_ram;
+        variable myram : p_ram;
+    begin
+        myram := new t_ram(0 to 31)(15 downto 0);
+        for i in myram'range loop
+            myram(i) := TO_UNSIGNED(i, 16);
+        end loop;
+        for i in myram'range loop
+            report integer'image(i) & ": " & TO_HSTRING(myram(i));
+        end loop;
+        wait;
+    end process DM;
+    
+end architecture TB;
diff --git a/testsuite/gna/issue473/testsuite.sh b/testsuite/gna/issue473/testsuite.sh
new file mode 100755
index 000000000..6a33b5970
--- /dev/null
+++ b/testsuite/gna/issue473/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze tbmem.vhdl
+elab_simulate tbmem
+
+clean
+
+echo "Test successful"
-- 
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