From 3bd4d200a891ac813d60aa6bd9d055f43da972d6 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 10 Nov 2018 07:46:16 +0100
Subject: Add testcase from #689

close #689
---
 testsuite/gna/issue689/example.vhdl | 37 +++++++++++++++++++++++++++++++++++++
 testsuite/gna/issue689/testsuite.sh | 11 +++++++++++
 2 files changed, 48 insertions(+)
 create mode 100644 testsuite/gna/issue689/example.vhdl
 create mode 100755 testsuite/gna/issue689/testsuite.sh

diff --git a/testsuite/gna/issue689/example.vhdl b/testsuite/gna/issue689/example.vhdl
new file mode 100644
index 000000000..6b40fa4a9
--- /dev/null
+++ b/testsuite/gna/issue689/example.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package test_pkg is
+  type my_array is array(natural range <>) of unsigned;
+end package test_pkg;
+
+--library vunit_lib;
+--context vunit_lib.vunit_context;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+use work.test_pkg.all;
+
+entity tb_example is
+  generic (runner_cfg : string := "x");
+end entity;
+
+architecture tb of tb_example is
+  constant DDR_DATA_WIDTH       : integer := 128;
+  constant FILTER_WORD_SIZE     : integer := 16;
+
+--  signal switch_out : my_array(0 to DDR_DATA_WIDTH / FILTER_WORD_SIZE - 1)(natural(log2(real(DDR_DATA_WIDTH / FILTER_WORD_SIZE))) - 1 downto 0);
+  signal switch_out : my_array(0 to 7)(2 downto 0);
+    
+begin
+  main : process
+  begin
+ --   test_runner_setup(runner, runner_cfg);
+    report "Hello world!";
+ --   test_runner_cleanup(runner); -- Simulation ends here
+    wait;
+  end process;
+end architecture;
diff --git a/testsuite/gna/issue689/testsuite.sh b/testsuite/gna/issue689/testsuite.sh
new file mode 100755
index 000000000..6163b63f7
--- /dev/null
+++ b/testsuite/gna/issue689/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze example.vhdl
+elab_simulate tb_example
+
+clean
+
+echo "Test successful"
-- 
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