From 3bbdbaf0c5789baf38f6e4c57e4c669f1d8e03a0 Mon Sep 17 00:00:00 2001
From: Patrick Lehmann <Patrick.Lehmann@plc2.de>
Date: Sat, 19 Jun 2021 02:54:31 +0200
Subject: Added testcase for integer literals.

---
 testsuite/pyunit/Current.vhdl      | 53 ++++++++++++++++++++++++++++++++++++++
 testsuite/pyunit/SimpleEntity.vhdl | 13 +++-------
 testsuite/pyunit/dom/Literals.py   | 48 ++++++++++++++++++++++++++++++++++
 3 files changed, 105 insertions(+), 9 deletions(-)
 create mode 100644 testsuite/pyunit/Current.vhdl
 create mode 100644 testsuite/pyunit/dom/Literals.py

diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
new file mode 100644
index 000000000..5a677546e
--- /dev/null
+++ b/testsuite/pyunit/Current.vhdl
@@ -0,0 +1,53 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+entity entity_1 is
+	generic (
+		FREQ : real     := 100.0;
+		BITS : positive := 8
+	);
+	port (
+	  Clock: in  std_logic;
+	  Reset: in  std_logic := '0';
+	  Q:     out std_logic_vector(BITS - 1 downto 0)
+	);
+
+	constant fire : boolean := True;
+begin
+	wood <= fire;
+end entity entity_1;
+
+architecture behav of entity_1 is
+	constant MAX : positive := -25;
+	signal rst : std_logic := 'U';
+
+	type newInt is range -4 to 3;
+	subtype uint8 is integer range 0 to 255;
+
+	function foo(a : integer; b : boolean) return bit is
+	begin
+
+	end function;
+
+	alias bar is boolean;
+begin
+	process(Clock)
+	begin
+		if rising_edge(Clock) then
+			if Reset = '1' then
+				Q <= (others => '0');
+			else
+				Q <= std_logic_vector(unsigned(Q) + 1);
+			end if;
+		end if;
+	end process;
+end architecture behav;
+
+package package_1 is
+	constant ghdl : float := (3, 5, 0 => 5, 3 => 4, name => 10); -- 2.3;
+end package;
+
+package body package_1 is
+	constant ghdl : float := (1); -- => 2, 4 => 5, others => 10); -- .5;
+end package body;
diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl
index 12068c06d..90d68fd83 100644
--- a/testsuite/pyunit/SimpleEntity.vhdl
+++ b/testsuite/pyunit/SimpleEntity.vhdl
@@ -15,11 +15,14 @@ entity entity_1 is
 end entity entity_1;
 
 architecture behav of entity_1 is
+	signal Reset_n : std_logic;
 begin
+	Reset_n <= not Reset;
+
 	process(Clock)
 	begin
 		if rising_edge(Clock) then
-			if Reset = '1' then
+			if Reset_n = '0' then
 				Q <= (others => '0');
 			else
 				Q <= std_logic_vector(unsigned(Q) + 1);
@@ -27,11 +30,3 @@ begin
 		end if;
 	end process;
 end architecture behav;
-
-package package_1 is
-	constant ghdl : float := (3, 5, 0 => 5, 3 => 4, name => 10); -- 2.3;
-end package;
-
-package body package_1 is
-	constant ghdl : float := (1); -- => 2, 4 => 5, others => 10); -- .5;
-end package body;
diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py
new file mode 100644
index 000000000..8e426a0a9
--- /dev/null
+++ b/testsuite/pyunit/dom/Literals.py
@@ -0,0 +1,48 @@
+from pyGHDL.dom.Literal import IntegerLiteral
+from pyGHDL.dom.Object import Constant
+from pathlib  import Path
+from textwrap import dedent
+from unittest import TestCase
+
+from pyGHDL.dom.Misc       import Design, Document
+
+if __name__ == "__main__":
+    print("ERROR: you called a testcase declaration file as an executable module.")
+    print("Use: 'python -m unitest <testcase module>'")
+    exit(1)
+
+
+class Literals(TestCase):
+    _root = Path(__file__).resolve().parent.parent
+
+    def test_IntegerLiteral(self):
+        self._filename: Path = self._root / "{className}.vhdl".format(className=self.__class__.__name__)
+
+        sourceCode = dedent("""\
+            package package_1 is
+              constant c0 : integer := 0;
+              constant c1 : integer := 1;
+              constant c2 : integer := 1024;
+              constant c3 : integer := 1048576;
+            end package;
+            """)
+        expected = (0, 1, 1024, 1048576)
+
+        with self._filename.open(mode="w", encoding="utf-8") as file:
+            file.write(sourceCode)
+
+        design = Design()
+        document = Document(self._filename)
+        design.Documents.append(document)
+
+        self.assertEqual(len(design.Documents[0].Packages), 1)
+        package = design.Documents[0].Packages[0]
+        self.assertTrue(package.Name == "package_1")
+        self.assertEqual(len(package.DeclaredItems), len(expected))
+        for i in range(len(expected)):
+            item: Constant = package.DeclaredItems[i]
+            self.assertTrue(isinstance(item, Constant))
+            self.assertTrue(item.Name == "c{}".format(i))
+            self.assertTrue(item.SubType.SymbolName == "integer")
+            self.assertTrue(isinstance(item.DefaultExpression, IntegerLiteral))
+            self.assertTrue(item.DefaultExpression.Value == expected[i])
-- 
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