From 301dea333ec3e28e95a43b1a4af569ebbedd6ab9 Mon Sep 17 00:00:00 2001
From: Patrick Lehmann <Patrick.Lehmann@plc2.de>
Date: Wed, 30 Jun 2021 13:52:30 +0200
Subject: Added package declarations inside of declarations. Added PSL Default
 clock (dummy). Added Disconnect specification (dummy).

---
 pyGHDL/dom/PSL.py                    | 21 +++++++++++++++++++++
 pyGHDL/dom/_Translate.py             | 11 +++++++++++
 pyGHDL/dom/formatting/prettyprint.py | 13 +++++++++++++
 testsuite/pyunit/Current.vhdl        |  9 ++++++++-
 4 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/pyGHDL/dom/PSL.py b/pyGHDL/dom/PSL.py
index dd859e5b3..6c4ba76b3 100644
--- a/pyGHDL/dom/PSL.py
+++ b/pyGHDL/dom/PSL.py
@@ -39,12 +39,14 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 
 
 """
+from pyGHDL.libghdl.vhdl import nodes
 from pydecor import export
 
 from pyVHDLModel.PSLModel import (
     VerificationUnit as VHDLModel_VerificationUnit,
     VerificationProperty as VHDLModel_VerificationProperty,
     VerificationMode as VHDLModel_VerificationMode,
+    DefaultClock as VHDLModel_DefaultClock,
 )
 
 from pyGHDL.libghdl._types import Iir
@@ -110,3 +112,22 @@ class VerificationMode(VHDLModel_VerificationMode, DOMMixin):
         # FIXME: needs an implementation
 
         return cls(vmodeNode, name)
+
+
+@export
+class DefaultClock(VHDLModel_DefaultClock, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, defaultClockNode: Iir):
+        name = GetNameOfNode(defaultClockNode)
+
+        # FIXME: needs an implementation
+
+        return cls(defaultClockNode, name)
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index 4e9515767..a9ead8c2c 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -36,6 +36,7 @@ from pydecor import export
 
 from pyGHDL.dom import Position, DOMException
 from pyGHDL.dom.Object import Variable
+from pyGHDL.dom.PSL import DefaultClock
 from pyVHDLModel.VHDLModel import (
     Constraint,
     Direction,
@@ -627,6 +628,10 @@ def GetDeclaredItemsFromChainedNodes(
             from pyGHDL.dom.DesignUnit import UseClause
 
             yield UseClause.parse(item)
+        elif kind == nodes.Iir_Kind.Package_Declaration:
+            from pyGHDL.dom.DesignUnit import Package
+
+            yield Package.parse(item)
         elif kind == nodes.Iir_Kind.Package_Instantiation_Declaration:
             from pyGHDL.dom.DesignUnit import PackageInstantiation
 
@@ -637,6 +642,8 @@ def GetDeclaredItemsFromChainedNodes(
                     name=name
                 )
             )
+        elif kind == nodes.Iir_Kind.Psl_Default_Clock:
+            yield DefaultClock.parse(item)
         elif kind == nodes.Iir_Kind.Group_Declaration:
             print("[NOT IMPLEMENTED] Group declaration in {name}".format(name=name))
         elif kind == nodes.Iir_Kind.Group_Template_Declaration:
@@ -645,6 +652,10 @@ def GetDeclaredItemsFromChainedNodes(
                     name=name
                 )
             )
+        elif kind == nodes.Iir_Kind.Disconnection_Specification:
+            print(
+                "[NOT IMPLEMENTED] Disconnect specification in {name}".format(name=name)
+            )
         else:
             position = Position.parse(item)
             raise DOMException(
diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py
index 4eef043f5..4d6e5dccb 100644
--- a/pyGHDL/dom/formatting/prettyprint.py
+++ b/pyGHDL/dom/formatting/prettyprint.py
@@ -4,6 +4,7 @@ from pydecor import export
 
 from pyGHDL.dom.Attribute import Attribute, AttributeSpecification
 from pyGHDL.dom.Misc import Alias
+from pyGHDL.dom.PSL import DefaultClock
 from pyGHDL.dom.Subprogram import Procedure
 from pyGHDL.dom.Type import (
     IntegerType,
@@ -478,12 +479,24 @@ class PrettyPrint:
             buffer.append(
                 "{prefix}- use {name!s}".format(prefix=prefix, name=item.Item)
             )
+        elif isinstance(item, Package):
+            buffer.append(
+                "{prefix}- package {name} is ..... end package".format(
+                    prefix=prefix, name=item.Identifier
+                )
+            )
         elif isinstance(item, PackageInstantiation):
             buffer.append(
                 "{prefix}- package {name} is new {name2!s} generic map (.....)".format(
                     prefix=prefix, name=item.Identifier, name2=item.PackageReference
                 )
             )
+        elif isinstance(item, DefaultClock):
+            buffer.append(
+                "{prefix}- default {name} is {expr}".format(
+                    prefix=prefix, name=item.Identifier, expr="..."
+                )
+            )
         else:
             raise PrettyPrintException(
                 "Unhandled declared item kind '{name}'.".format(
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index b2c7aff11..93474000b 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -77,6 +77,13 @@ architecture behav of entity_1 is
 	attribute att : boolean;
 
 	alias bar is boolean;
+
+	disconnect address_bus : resolved_word after 3 ns;
+	disconnect others : resolved_word after 2 ns;
+
+	default clock is rising_edge(clk);
+	package inner_pack is
+	end package;
 begin
 	process(Clock)
 	begin
@@ -100,7 +107,7 @@ package package_1 is
   type cell;
 
 	constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10); -- 2.3;
-	attribute fixed of ghdl [bar] : constant is true;
+	attribute fixed of ghdl, gtkwave [x, y] : constant is true;
 
 	component comp is
 		port (
-- 
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