From 2b3e933a016f31417080a3dd43e9925249e4b76f Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 29 Jul 2019 18:44:40 +0200 Subject: synth: add arr02 test. --- testsuite/synth/arr02/rom1.vhdl | 19 +++++++++++++++++++ testsuite/synth/arr02/tb_rom1.vhdl | 38 ++++++++++++++++++++++++++++++++++++++ testsuite/synth/arr02/testsuite.sh | 16 ++++++++++++++++ 3 files changed, 73 insertions(+) create mode 100644 testsuite/synth/arr02/rom1.vhdl create mode 100644 testsuite/synth/arr02/tb_rom1.vhdl create mode 100755 testsuite/synth/arr02/testsuite.sh diff --git a/testsuite/synth/arr02/rom1.vhdl b/testsuite/synth/arr02/rom1.vhdl new file mode 100644 index 000000000..6b8245f30 --- /dev/null +++ b/testsuite/synth/arr02/rom1.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity rom1 is + port (addr : std_logic_vector (3 downto 0); + val : out std_logic_vector (7 downto 0)); +end rom1; + +architecture behav of rom1 is + type t_myrom is array (0 to 15) of std_logic_vector (7 downto 0); + constant myrom : t_myrom := + (x"00", x"01", x"02", x"03", + x"40", x"41", x"42", x"43", + x"f8", x"f9", x"fa", x"fb", + x"fc", x"fd", x"fe", x"ff"); +begin + val <= myrom (to_integer(unsigned(addr))); +end behav; diff --git a/testsuite/synth/arr02/tb_rom1.vhdl b/testsuite/synth/arr02/tb_rom1.vhdl new file mode 100644 index 000000000..4a7f96d29 --- /dev/null +++ b/testsuite/synth/arr02/tb_rom1.vhdl @@ -0,0 +1,38 @@ +entity tb_rom1 is +end tb_rom1; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_rom1 is + signal addr : std_logic_vector(3 downto 0); + signal dat : std_logic_vector(7 downto 0); +begin + dut: entity work.rom1 + port map (addr, dat); + + process + begin + addr <= "0000"; + wait for 1 ns; + assert dat = x"00" severity failure; + + addr <= "0101"; + wait for 1 ns; + assert dat = x"41" severity failure; + + addr <= "1100"; + wait for 1 ns; + assert dat = x"fc" severity failure; + + addr <= "1011"; + wait for 1 ns; + assert dat = x"fb" severity failure; + + addr <= "0010"; + wait for 1 ns; + assert dat = x"02" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/arr02/testsuite.sh b/testsuite/synth/arr02/testsuite.sh new file mode 100755 index 000000000..75e5794a7 --- /dev/null +++ b/testsuite/synth/arr02/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in rom1; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" -- cgit v1.2.3