From 2170c6f1592156b51254f30e2c4d0019fc91855b Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 3 Nov 2019 07:42:21 +0100 Subject: testsuite/synth: add test for tgingold/ghdlsynth-beta#56 --- testsuite/synth/synth56/tb_test2.vhdl | 26 ++++++++++++++++++++++++++ testsuite/synth/synth56/test2.vhdl | 16 ++++++++++++++++ testsuite/synth/synth56/testsuite.sh | 16 ++++++++++++++++ 3 files changed, 58 insertions(+) create mode 100644 testsuite/synth/synth56/tb_test2.vhdl create mode 100644 testsuite/synth/synth56/test2.vhdl create mode 100755 testsuite/synth/synth56/testsuite.sh diff --git a/testsuite/synth/synth56/tb_test2.vhdl b/testsuite/synth/synth56/tb_test2.vhdl new file mode 100644 index 000000000..3403d30db --- /dev/null +++ b/testsuite/synth/synth56/tb_test2.vhdl @@ -0,0 +1,26 @@ +entity tb_test2 is +end tb_test2; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_test2 is + signal v : std_logic_vector(1 downto 0); + signal s : std_logic_vector(1 downto 0); +begin + dut: entity work.test2 + port map (s, v); + + process + begin + s <= "00"; + wait for 1 ns; + assert v = "00" severity failure; + + s <= "11"; + wait for 1 ns; + assert v = "10" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/synth56/test2.vhdl b/testsuite/synth/synth56/test2.vhdl new file mode 100644 index 000000000..09c82d189 --- /dev/null +++ b/testsuite/synth/synth56/test2.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test2 is + port ( + d_in: in std_logic_vector(1 downto 0); + d_out: out std_logic_vector(1 downto 0) + ); +end entity test2; + +architecture rtl of test2 is + constant c : std_logic_vector (7 downto 0) := "10010000"; +begin + d_out <= c(to_integer(unsigned(d_in))+1 downto to_integer(unsigned(d_in))); +end rtl; diff --git a/testsuite/synth/synth56/testsuite.sh b/testsuite/synth/synth56/testsuite.sh new file mode 100755 index 000000000..6ab61cc2b --- /dev/null +++ b/testsuite/synth/synth56/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in test2; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean +done + +echo "Test successful" -- cgit v1.2.3