From 20da7909751eb191e6c77bed5fc5b6bc0d7374f1 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 8 Oct 2019 06:29:20 +0200
Subject: testsuite/synth: add a test.

---
 testsuite/synth/dff02/dff06.vhdl    | 22 +++++++++++++++++
 testsuite/synth/dff02/tb_dff06.vhdl | 49 +++++++++++++++++++++++++++++++++++++
 testsuite/synth/dff02/testsuite.sh  | 16 ++++++++++++
 3 files changed, 87 insertions(+)
 create mode 100644 testsuite/synth/dff02/dff06.vhdl
 create mode 100644 testsuite/synth/dff02/tb_dff06.vhdl
 create mode 100755 testsuite/synth/dff02/testsuite.sh

diff --git a/testsuite/synth/dff02/dff06.vhdl b/testsuite/synth/dff02/dff06.vhdl
new file mode 100644
index 000000000..a8cad2c04
--- /dev/null
+++ b/testsuite/synth/dff02/dff06.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff06 is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic;
+        rst : std_logic);
+end dff06;
+
+architecture behav of dff06 is
+  signal p : std_logic_vector(7 downto 0);
+begin
+  process (clk, rst) is
+  begin
+    if rst = '1' then
+      p <= x"00";
+    elsif rising_edge (clk) then
+      q <= d;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/tb_dff06.vhdl b/testsuite/synth/dff02/tb_dff06.vhdl
new file mode 100644
index 000000000..2d407a13c
--- /dev/null
+++ b/testsuite/synth/dff02/tb_dff06.vhdl
@@ -0,0 +1,49 @@
+entity tb_dff06 is
+end tb_dff06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff06 is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff06
+    port map (
+      q => dout,
+      d => din,
+      clk => clk,
+      rst => rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '0';
+    din <= x"7e";
+    pulse;
+    assert dout = x"7e" severity failure;
+
+    din <= x"38";
+    pulse;
+    assert dout = x"38" severity failure;
+
+    rst <= '1';
+    din <= x"af";
+    pulse;
+    assert dout = x"38" severity failure;
+
+    rst <= '0';
+    pulse;
+    assert dout = x"af" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/testsuite.sh b/testsuite/synth/dff02/testsuite.sh
new file mode 100755
index 000000000..dae869ec7
--- /dev/null
+++ b/testsuite/synth/dff02/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in dff06; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"
-- 
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