From 1989110a760403d7067936c98a22ea1eb0db2ab0 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 11 Jan 2023 05:29:05 +0100 Subject: simul: improve support of psl in debugger --- src/synth/elab-vhdl_debug.adb | 3 +++ src/vhdl/vhdl-sem_scopes.adb | 14 ++++++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/synth/elab-vhdl_debug.adb b/src/synth/elab-vhdl_debug.adb index 680f345ac..d9b14f75f 100644 --- a/src/synth/elab-vhdl_debug.adb +++ b/src/synth/elab-vhdl_debug.adb @@ -560,6 +560,9 @@ package body Elab.Vhdl_Debug is | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Simple_Simultaneous_Statement => null; + when Iir_Kind_Psl_Default_Clock + | Iir_Kind_Psl_Assert_Directive => + null; when Iir_Kinds_Process_Statement => -- Note: processes are not elaborated. if Cfg.With_Objs then diff --git a/src/vhdl/vhdl-sem_scopes.adb b/src/vhdl/vhdl-sem_scopes.adb index fcc2707fa..4a4f65f64 100644 --- a/src/vhdl/vhdl-sem_scopes.adb +++ b/src/vhdl/vhdl-sem_scopes.adb @@ -1289,10 +1289,16 @@ package body Vhdl.Sem_Scopes is begin El := Get_Concurrent_Statement_Chain (Parent); while El /= Null_Iir loop - Label := Get_Label (El); - if Label /= Null_Identifier then - Add_Name (El, Get_Identifier (El), False); - end if; + case Get_Kind (El) is + when Iir_Kind_Psl_Default_Clock => + -- Not a statement with label. + null; + when others => + Label := Get_Label (El); + if Label /= Null_Identifier then + Add_Name (El, Get_Identifier (El), False); + end if; + end case; El := Get_Chain (El); end loop; end Add_Declarations_Of_Concurrent_Statement; -- cgit v1.2.3