From 185f0db95d1e683deb053e25766e1d934cbd5b14 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 29 Jun 2022 07:31:30 +0200
Subject: testsuite/gna: improve test #2115

---
 testsuite/gna/issue2115/testsuite.sh | 15 ++++++++-------
 testsuite/gna/issue2115/tst08.vhdl   | 24 ++++++++++++++++++++++++
 testsuite/gna/issue2115/tst93.vhdl   | 21 +++++++++++++++++++++
 3 files changed, 53 insertions(+), 7 deletions(-)
 create mode 100644 testsuite/gna/issue2115/tst08.vhdl
 create mode 100644 testsuite/gna/issue2115/tst93.vhdl

diff --git a/testsuite/gna/issue2115/testsuite.sh b/testsuite/gna/issue2115/testsuite.sh
index c562f1efd..9fbe06a6c 100755
--- a/testsuite/gna/issue2115/testsuite.sh
+++ b/testsuite/gna/issue2115/testsuite.sh
@@ -4,15 +4,16 @@
 
 export GHDL_STD_FLAGS=--std=08
 analyze ent.vhdl
-elab_simulate ent > ent.out
+elab_simulate ent
 
-if grep TRUE ent.out; then
-  exit 1
-fi
+analyze tst08.vhdl
+elab_simulate tst08
 
-if grep FALSE ent.out; then
-  exit 1
-fi
+clean
+
+export GHDL_STD_FLAGS=--std=93
+analyze tst93.vhdl
+elab_simulate tst93
 
 clean
 
diff --git a/testsuite/gna/issue2115/tst08.vhdl b/testsuite/gna/issue2115/tst08.vhdl
new file mode 100644
index 000000000..57ccfda2a
--- /dev/null
+++ b/testsuite/gna/issue2115/tst08.vhdl
@@ -0,0 +1,24 @@
+entity tst08 is
+end entity;
+
+use std.textio.all;
+
+architecture a of tst08 is
+begin
+  process
+    variable l : line;
+  begin
+    write(l, false);
+    assert l.all = "false" severity failure;
+    deallocate (l);
+    write(l, true);
+    assert l.all = "true" severity failure;
+
+    assert boolean'image(true) = "true" severity failure;
+    assert boolean'image(false) = "false" severity failure;
+
+    assert to_string(true) = "true" severity failure;
+    assert to_string(false) = "false" severity failure;
+    wait;
+  end process;
+end;
diff --git a/testsuite/gna/issue2115/tst93.vhdl b/testsuite/gna/issue2115/tst93.vhdl
new file mode 100644
index 000000000..5fb36fbb8
--- /dev/null
+++ b/testsuite/gna/issue2115/tst93.vhdl
@@ -0,0 +1,21 @@
+entity tst93 is
+end entity;
+
+use std.textio.all;
+
+architecture a of tst93 is
+begin
+  process
+    variable l : line;
+  begin
+    write(l, false);
+    assert l.all = "FALSE" severity failure;
+    deallocate (l);
+    write(l, true);
+    assert l.all = "TRUE" severity failure;
+
+    assert boolean'image(true) = "true" severity failure;
+    assert boolean'image(false) = "false" severity failure;
+    wait;
+  end process;
+end;
-- 
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