From 11ed6c6f88a063894a114af97c5a8e84bb730927 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 13 Dec 2017 21:08:10 +0100 Subject: hack doc and regenerate texi file. --- doc/Makefile | 44 +- doc/conf.py | 25 +- doc/ghdl.texi | 6315 +++++++++++++++++++++++++++++++++++++--------------- doc/index.rst | 4 +- doc/shields.inc | 9 +- doc/shieldswho.inc | 24 +- 6 files changed, 4595 insertions(+), 1826 deletions(-) diff --git a/doc/Makefile b/doc/Makefile index eb08aa6b1..4fbaadc3f 100644 --- a/doc/Makefile +++ b/doc/Makefile @@ -1,14 +1,33 @@ -SRC_FILES= \ - Copyrights.rst \ - Flaws_and_bugs_report.rst \ - GHDL_implementation_of_VHDL.rst \ - GHDL_implementation_of_VITAL.rst \ - Introduction.rst \ - Invoking_GHDL.rst \ - Simulation_and_runtime.rst \ - Starting_with_GHDL.rst \ - index.rst \ - conf.py +SRCS= \ +conf.py \ +prolog.inc shields.inc shieldswho.inc \ +about.rst \ +appendix/Meta.rst appendix/Roadmap.rst \ +building/Building.rst \ +building/Directories.rst \ +building/gcc/GNULinux-GNAT.rst \ +building/gcc/index.rst \ +building/gcc/Windows-MinGW-GNAT.rst \ +building/llvm/GNULinux-GNAT.rst \ +building/llvm/index.rst \ +building/llvm/Windows-MinGW-GNAT.rst \ +building/mcode/GNULinux-GNAT.rst \ +building/mcode/index.rst \ +building/mcode/Windows-GNATGPL.rst \ +building/mcode/Windows-MinGW-GNAT.rst \ +building/PrecompileVendorPrimitives.rst \ +contribute.rst \ +genindex.rst \ +getting/Releases.rst \ +index.rst \ +licenses.rst \ +references/CodingStyle.rst \ +references/CommandReference.rst \ +references/ImplementationOfVHDL.rst \ +references/ImplementationOfVITAL.rst \ +using/InvokingGHDL.rst \ +using/QuickStartGuide.rst \ +using/Simulation.rst CP=cp @@ -42,7 +61,8 @@ ghdl.pdf: ghdl.dvi html: $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html -ghdl.texi: $(SRC_FILES) +texi: ghdl.texi +ghdl.texi: $(SRCS) $(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo $(CP) $(BUILDDIR)/texinfo/GHDL.texi $@ diff --git a/doc/conf.py b/doc/conf.py index 3374b63e0..9c64a6ff6 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -76,25 +76,12 @@ author = u'Tristan Gingold and contributors' # |version| and |release|, also used in various other places throughout the # built documents. # -def _IsUnderGitControl(): - return (subprocess.check_output(["git", "rev-parse", "--is-inside-work-tree"], universal_newlines=True).strip() == "true") - -def _LatestTagName(): - return subprocess.check_output(["git", "describe", "--abbrev=0", "--tags"], universal_newlines=True).strip() - try: - if _IsUnderGitControl: - descr = _LatestTagName() - if descr.startswith('v'): - version = descr[1:] # remove prefix "v" - else: - version = descr - else: - with open('../src/version.in') as verin: - for line in verin: - line = re.findall(r'Ghdl_Ver.+\"(.+)\";', line) - if line: - version=line[0] + with open('../src/version.in') as verin: + for line in verin: + line = re.findall(r'Ghdl_Ver.+\"(.+)\";', line) + if line: + version=line[0] except Exception, e: print "cannot extract version: %s" % e version = "latest" @@ -362,4 +349,4 @@ extlinks = { 'ghdlissue': ('https://github.com/tgingold/ghdl/issues/%s', 'issue #'), 'ghdlpull': ('https://github.com/tgingold/ghdl/pull/%s', 'pull request #'), 'ghdlsrc': ('https://github.com/tgingold/ghdl/blob/master/src/%s', None) -} \ No newline at end of file +} diff --git a/doc/ghdl.texi b/doc/ghdl.texi index f686f6a4e..1bfc3c603 100644 --- a/doc/ghdl.texi +++ b/doc/ghdl.texi @@ -3,7 +3,7 @@ @setfilename GHDL.info @documentencoding UTF-8 @ifinfo -@*Generated by Sphinx 1.3.5.@* +@*Generated by Sphinx 1.6.5.@* @end ifinfo @settitle GHDL Documentation @defindex ge @@ -21,11 +21,11 @@ @copying @quotation -GHDL 2016-09-14, February 18, 2017 +GHDL 0.35-dev, Dec 13, 2017 -Tristan Gingold +Tristan Gingold and contributors -Copyright @copyright{} 2015, Tristan Gingold +Copyright @copyright{} 2015-2017, Tristan Gingold and contributors @end quotation @end copying @@ -48,112 +48,256 @@ Copyright @copyright{} 2015, Tristan Gingold @c %**start of body @anchor{index doc}@anchor{0} -@c GHDL documentation master file, created by -@c sphinx-quickstart on Fri Nov 20 20:33:03 2015. -@c You can adapt this file completely to your liking, but it should at least -@c contain the root `toctree` directive. +@c # preload commonly known graphical characters like (c) + +@c This data file has been placed in the public domain. + +@c Derived from the Unicode character mappings available from +@c . +@c Processed by unicode2rstsubs.py, part of Docutils: +@c . + +@c # define a hard kine break for HTML + +@c # This file provides the following shields: travis-ci appveyor release +@c # license mailing gitter issues-new issues-open issues-closed issues-pr +@c # issues-pr-closed github gh-logo + +@c # Use http://b64.io/ to encode any image to base64. Then replace `/` with +@c # `%2F` and `+` with `%2B` (or use http://meyerweb.com/eric/tools/dencoder/). +@c # Beware that `?logo=data:image/png;base64,` must also be converted to +@c # percent encoding so that the URL is properly parsed. + + + + + + +__________________________________________________________________ + + +This manual is the user and reference manual for GHDL. It does not contain an +introduction to VHDL. Thus, the reader should have at least a basic knowledge +of VHDL. A good knowledge of VHDL language reference manual (usually called +LRM) is a plus. + + + +This document was generated on Dec 13, 2017 - 20:49. + +@c # preload commonly known graphical characters like (c) + +@c This data file has been placed in the public domain. + +@c Derived from the Unicode character mappings available from +@c . +@c Processed by unicode2rstsubs.py, part of Docutils: +@c . + +@c # define a hard kine break for HTML + + + + -Contents: @menu -* Introduction:: -* Starting with GHDL:: +* About GHDL:: +* Contributing:: +* Copyrights | Licenses:: +* Quick Start Guide:: * Invoking GHDL:: * Simulation and runtime:: -* GHDL implementation of VHDL:: -* GHDL implementation of VITAL:: -* Flaws and bugs report:: -* Copyrights:: -* Indices and tables:: +* Releases and sources:: +* Building GHDL from Sources:: +* Precompile Vendor Primitives:: +* Command Reference:: +* Coding Style:: +* Implementation of VHDL:: +* Implementation of VITAL:: +* Roadmap | Future Improvements:: +* Meta:: +* Index: Index<2>. * Index:: @detailmenu --- The Detailed Node Listing --- -Introduction +About GHDL -* Content of this manual:: * What is VHDL?:: * What is GHDL?:: +* Who uses GHDL?:: -Starting with GHDL +Contributing -* The hello world program:: +* Reporting bugs:: +* Requesting enhancements:: +* Improving the documentation:: +* Fork@comma{} modify and pull-request: Fork modify and pull-request. +* Related interesting projects:: + +Copyrights | Licenses + +* GNU GPLv2:: +* CC-BY-SA:: +* List of Contributors:: + +Quick Start Guide + +* The ‘Hello world’ program:: +* The heartbeat program:: * A full adder:: * Starting with a design:: Invoking GHDL -* Building commands:: -* GHDL options:: -* Passing options to other programs:: -* GHDL Diagnostics Control:: -* GHDL warnings:: -* Rebuilding commands:: +* Design building commands:: +* Design rebuilding commands:: +* Options:: +* Warnings:: +* Diagnostics Control:: * Library commands:: -* Cross-reference command:: -* File commands:: -* Misc commands:: * VPI build commands:: -* Installation Directory:: * IEEE library pitfalls:: -* IEEE math packages:: -Building commands +Design building commands -* Analysis command:: -* Elaboration command:: -* Run command:: -* Elaborate and run command:: -* Bind command:: -* Link command:: -* List link command:: -* Check syntax command:: -* Analyze and elaborate command:: +* Analysis [-a]:: +* Elaboration [-e]:: +* Run [-r]:: +* Elaborate and run [--elab-run]:: +* Check syntax [-s]:: +* Analyze and elaborate [-c]:: -Rebuilding commands +Design rebuilding commands -* Import command:: -* Make command:: -* Generate Makefile command:: +* Import [-i]:: +* Make [-m]:: +* Generate Makefile [--gen-makefile]:: +* Generate dependency file command [--gen-depends]:: Library commands -* Directory command:: -* Clean command:: -* Remove command:: -* Copy command:: -* Create a Library:: +* Directory [--dir]:: +* Clean [--clean]:: +* Remove [--remove]:: +* Copy [--copy]:: -File commands +VPI build commands + +* compile [--vpi-compile]:: +* link [--vpi-link]:: +* cflags [--vpi-cflags]:: +* ldflags [--vpi-ldflags]:: +* include dir [--vpi-include-dir]:: +* library dir [--vpi-library-dir]:: + +Simulation and runtime + +* Simulation options:: +* Export waveforms:: +* Export hierarchy and references:: +* Debugging:: + +Debugging + +* GNU Debugger (GDB): GNU Debugger GDB. + +Releases and sources + +* Downloading pre-built packages:: +* Downloading Source Files:: + +Downloading Source Files + +* Downloading from GitHub:: +* Downloading via git clone:: + +Downloading via git clone + +* On Linux:: +* On OS X:: +* On Windows:: + +Building GHDL from Sources + +* Directory Structure:: +* mcode Backend:: +* LLVM Backend:: +* GCC Backend:: + +mcode Backend + +* GHDL with mcode backend build on GNU/Linux with GCC/GNAT:: +* GHDL with mcode backend build on Windows with GNAT GPL:: +* GHDL with mcode backend build on Windows with GCC/GNAT (MinGW): GHDL with mcode backend build on Windows with GCC/GNAT MinGW. + +GHDL with mcode backend build on Windows with GNAT GPL + +* Requirements:: +* Scripts and Parameters:: + +Scripts and Parameters + +* compile.ps1: compile ps1. + +LLVM Backend + +* GNU/Linux with GCC/GNAT:: +* GHDL with LLVM backend build on Windows with GCC/GNAT (MinGW): GHDL with LLVM backend build on Windows with GCC/GNAT MinGW. + +GCC Backend + +* GNU/Linux with GCC/GNAT: GNU/Linux with GCC/GNAT<2>. +* GHDL with GCC backend build on Windows with GCC/GNAT (MinGW): GHDL with GCC backend build on Windows with GCC/GNAT MinGW. + +Precompile Vendor Primitives + +* Supported Vendors Libraries:: +* Supported Simulation and Verification Libraries:: +* Script Configuration:: +* Compiling on Linux:: +* Compiling on Windows:: +* Configuration Files:: + +Configuration Files + +* For Linux; config.sh: For Linux config sh. +* For Windows; config.psm1: For Windows config psm1. +* Selectable Options for the Bash Scripts;: Selectable Options for the Bash Scripts. +* Selectable Options for the PowerShell Scripts;: Selectable Options for the PowerShell Scripts. + +Command Reference -* Pretty print command:: -* Find command:: -* Chop command:: -* Lines command:: +* Environment variables:: +* Misc commands:: +* File commands:: +* GCC/LLVM only commands:: +* Options: Options<2>. +* Passing options to other programs:: Misc commands -* Help command:: -* Disp config command:: -* Disp standard command:: -* Version command:: +* Help [-h]:: +* Display config [--disp-config]:: +* Display standard [--disp-standard]:: +* Version [--version]:: -VPI build commands +File commands -* VPI compile command:: -* VPI link command:: -* VPI cflags command:: -* VPI ldflags command:: -* VPI include dir command:: -* VPI library dir command:: +* Pretty print [--pp-html]:: +* Find [-f]:: +* Chop [--chop]:: +* Lines [--lines]:: -Simulation and runtime +GCC/LLVM only commands -* Simulation options:: -* Debugging VHDL programs:: +* Bind [--bind]:: +* Link [--link]:: +* List link [--list-link]:: -GHDL implementation of VHDL +Implementation of VHDL * VHDL standards:: * PSL implementation:: @@ -172,1937 +316,1926 @@ Interfacing to other languages * Linking with Ada:: * Using GRT from Ada:: -GHDL implementation of VITAL +Implementation of VITAL * VITAL packages:: * VHDL restrictions for VITAL:: * Backannotation:: * Negative constraint calculation:: -Flaws and bugs report +Meta -* Reporting bugs:: -* Future improvements:: +* General guidelines to edit the documentation:: +* Guidelines to edit section ‘Building’:: +* Documentation configuration:: +* CSS:: +* Dist:: @end detailmenu @end menu -@node Introduction,Starting with GHDL,Top,Top -@anchor{Introduction welcome-to-ghdl-s-documentation}@anchor{1}@anchor{Introduction introduction}@anchor{2}@anchor{Introduction doc}@anchor{3} -@chapter Introduction +@node About GHDL,Contributing,Top,Top +@anchor{about ghdl-documentation}@anchor{1}@anchor{about doc}@anchor{2}@anchor{about about-ghdl}@anchor{3} +@chapter About GHDL @menu -* Content of this manual:: * What is VHDL?:: * What is GHDL?:: +* Who uses GHDL?:: @end menu -@node Content of this manual,What is VHDL?,,Introduction -@anchor{Introduction content-of-this-manual}@anchor{4} -@section Content of this manual - - -This manual is the user and reference manual for GHDL. It does not -contain an introduction to VHDL. Thus, the reader should have at least -a basic knowledge of VHDL. A good knowledge of VHDL language reference -manual (usually called LRM) is a plus. - -@node What is VHDL?,What is GHDL?,Content of this manual,Introduction -@anchor{Introduction what-is-vhdl}@anchor{5} +@node What is VHDL?,What is GHDL?,,About GHDL +@anchor{about intro-vhdl}@anchor{4}@anchor{about what-is-vhdl}@anchor{5} @section What is @cite{VHDL}? -@cite{VHDL} is an acronym for Very High Speed Integrated Circuit Hardware -Description Language which is a programming language used to describe a -logic circuit by function, data flow behaviour, or structure. +VHDL@footnote{https://en.wikipedia.org/wiki/VHDL} is an acronym for Very High Speed Integrated Circuit (VHSIC@footnote{https://en.wikipedia.org/wiki/VHSIC}) Hardware Description Language (HDL@footnote{https://en.wikipedia.org/wiki/HDL}), which is a programming language used to describe a logic circuit by function, data flow behavior, or structure. -@cite{VHDL} @emph{is} a programming language: although @cite{VHDL} was -not designed for writing general purpose programs, you can write any -algorithm with the @cite{VHDL} language. If you are able to write -programs, you will find in @cite{VHDL} features similar to those found -in procedural languages such as @cite{C}, @cite{Python}, or @cite{Ada}. -@cite{VHDL} derives most of its syntax and semantics from @cite{Ada}. -Knowing @cite{Ada} is an advantage for learning @cite{VHDL} (it is an -advantage in general as well). +Although VHDL was not designed for writing general purpose programs, VHDL @emph{is} a programming language, and you can write any algorithm with it. If you are able to write programs, you will find in VHDL features similar to those found in procedural languages such as @cite{C}, @cite{Python}, or @cite{Ada}. Indeed, VHDL derives most of its syntax and semantics from Ada. Knowing @cite{Ada} is an advantage for learning VHDL (it is an advantage in general as well). -However, @cite{VHDL} was not designed as a general purpose language but as an -@cite{HDL} (hardware description language). As the name implies, @cite{VHDL} -aims at modeling or documenting electronics systems. Due to the nature -of hardware components which are always running, @cite{VHDL} is a highly -concurrent language, built upon an event-based timing model. +However, VHDL was not designed as a general purpose language but as an @cite{HDL}. As the name implies, VHDL aims at modeling or documenting electronics systems. Due to the nature of hardware components which are always running, VHDL is a highly concurrent language, built upon an event-based timing model. -Like a program written in any other language, a @cite{VHDL} program -can be executed. Since @cite{VHDL} is used to model designs, the term -@emph{simulation} is often used instead of @cite{execution}, with the -same meaning. +Like a program written in any other language, a VHDL program can be executed. Since VHDL is used to model designs, the term @emph{simulation} is often used instead of @cite{execution}, with the same meaning. At the same time, like a design written in another @cite{HDL}, a set of VHDL sources can be transformed with a @emph{synthesis tool} into a netlist, that is, a detailed gate-level implementation. -Like a program written in another hardware description language, a -@cite{VHDL} program can be transformed with a @emph{synthesis tool} -into a netlist, that is, a detailed gate-level implementation. +The development of VHDL started in 1983 and the standard is named IEEE@footnote{https://www.ieee.org/} @cite{1076}. Four revisions exist: 1987@footnote{http://ieeexplore.ieee.org/document/26487/}, 1993@footnote{http://ieeexplore.ieee.org/document/392561/}, 2002@footnote{http://ieeexplore.ieee.org/document/1003477/} and 2008@footnote{http://ieeexplore.ieee.org/document/4772740/}. The standardization is handled by the VHDL Analysis and Standardization Group (VASG/P1076@footnote{http://www.eda-twiki.org/vasg/}). -@node What is GHDL?,,What is VHDL?,Introduction -@anchor{Introduction what-is-ghdl}@anchor{6} -@section What is @cite{GHDL}? +@node What is GHDL?,Who uses GHDL?,What is VHDL?,About GHDL +@anchor{about what-is-ghdl}@anchor{6}@anchor{about intro-ghdl}@anchor{7} +@section What is GHDL? -@cite{GHDL} is a shorthand for G Hardware Design Language. Currently, -@cite{G} has no meaning. +@cite{GHDL} is a shorthand for @cite{G Hardware Design Language} (currently, @cite{G} has no meaning). It is a VHDL compiler that can execute (nearly) any VHDL program. GHDL is @emph{not} a synthesis tool: you cannot create a netlist with GHDL (yet). -@cite{GHDL} is a @cite{VHDL} compiler that can execute (nearly) any -@cite{VHDL} program. @cite{GHDL} is @emph{not} a synthesis tool: you cannot -create a netlist with @cite{GHDL}. +Unlike some other simulators, GHDL is a compiler: it directly translates a VHDL file to machine code, without using an intermediary language such as @cite{C} or @cite{C++}. Therefore, the compiled code should be faster and the analysis time should be shorter than with a compiler using an intermediary language. -Unlike some other simulators, @cite{GHDL} is a compiler: it directly -translates a @cite{VHDL} file to machine code, using the @cite{GCC} or @cite{LLVM} -back-end and without using an intermediary language such as @cite{C} -or @cite{C++}. Therefore, the compiled code should be faster and -the analysis time should be shorter than with a compiler using an -intermediary language. +GHDL can use multiple back-ends, i.e. code generators, (GCC@footnote{http://gcc.gnu.org/}, LLVM@footnote{http://llvm.org/} or x86@footnote{https://en.wikipedia.org/wiki/X86-64}/i386@footnote{https://en.wikipedia.org/wiki/Intel_80386} only, a built-in one) and runs on GNU/Linux@footnote{https://en.wikipedia.org/wiki/Linux_distribution}, Windows@footnote{https://en.wikipedia.org/wiki/Microsoft_Windows} ™ and macOS@footnote{https://en.wikipedia.org/wiki/MacOS} ™ , both on x86 and on x86_64. -The Windows(TM) version of @cite{GHDL} is not based on @cite{GCC} but on -an internal code generator. +The current version of GHDL does not contain any graphical viewer: you cannot see signal waves. You can still check the behavior of your design with a test bench. Moreover, the current version can produce a GHW@footnote{http://ghdl.readthedocs.io/en/latest/using/Simulation.html?highlight=GHW#cmdoption-wave}, VCD@footnote{https://en.wikipedia.org/wiki/Value_change_dump} or @cite{FST} files which can be viewed with a waveform viewer@footnote{https://en.wikipedia.org/wiki/Waveform_viewer}, such as GtkWave@footnote{http://gtkwave.sourceforge.net/}. -The current version of @cite{GHDL} does not contain any graphical -viewer: you cannot see signal waves. You can still check with a test -bench. The current version can produce a @cite{VCD} file which can be -viewed with a wave viewer, as well as @cite{ghw} files to be viewed by -@cite{gtkwave}. +GHDL aims at implementing VHDL as defined by IEEE 1076@footnote{http://ieeexplore.ieee.org/document/4772740/}. It supports the 1987@footnote{http://ieeexplore.ieee.org/document/26487/}, 1993@footnote{http://ieeexplore.ieee.org/document/392561/} and 2002@footnote{http://ieeexplore.ieee.org/document/1003477/} revisions and, partially, the latest, 2008@footnote{http://ieeexplore.ieee.org/document/4772740/}. PSL@footnote{https://en.wikipedia.org/wiki/Property_Specification_Language} is also partially supported. -@cite{GHDL} aims at implementing @cite{VHDL} as defined by IEEE 1076. -It supports most of the 1987 standard and most features added by the -1993 standard. +Several third party projects are supported: VUnit@footnote{https://vunit.github.io/}, OSVVM@footnote{http://osvvm.org/}, cocotb@footnote{https://github.com/potentialventures/cocotb} (through the VPI interface@footnote{https://en.wikipedia.org/wiki/Verilog_Procedural_Interface}), … -@node Starting with GHDL,Invoking GHDL,Introduction,Top -@anchor{Starting_with_GHDL doc}@anchor{7}@anchor{Starting_with_GHDL starting-with-ghdl}@anchor{8} -@chapter Starting with GHDL +@node Who uses GHDL?,,What is GHDL?,About GHDL +@anchor{about intro-who}@anchor{8}@anchor{about who-uses-ghdl}@anchor{9} +@section Who uses GHDL? -In this chapter, you will learn how to use the GHDL compiler by -working on two examples. -@menu -* The hello world program:: -* A full adder:: -* Starting with a design:: +@multitable {xxxxxxxxxxxxxxxxxxxxx} {xxxxxxxxxxxxxxxxxxxxxx} {xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx} {xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx} +@headitem -@end menu +Project hub -@node The hello world program,A full adder,,Starting with GHDL -@anchor{Starting_with_GHDL the-hello-world-program}@anchor{9} -@section The hello world program +@tab +Documentation -To illustrate the large purpose of VHDL, here is a commented VHDL -"Hello world" program. +@tab -@example --- Hello world program. -use std.textio.all; -- Imports the standard textio package. +Name --- Defines a design entity, without any ports. -entity hello_world is -end hello_world; +@tab -architecture behaviour of hello_world is -begin - process - variable l : line; - begin - write (l, String'("Hello world!")); - writeline (output, l); - wait; - end process; -end behaviour; -@end example +Brief description -Suppose this program is contained in the file @code{hello.vhdl}. -First, you have to compile the file; this is called @cite{analysis} of a design -file in VHDL terms. +@item -@example -$ ghdl -a hello.vhdl -@end example +>>|SHIELD:gh-poc|<< -This command creates or updates a file @code{work-obj93.cf}, which -describes the library @cite{work}. On GNU/Linux, this command generates a -file @code{hello.o}, which is the object file corresponding to your -VHDL program. The object file is not created on Windows. +@tab -Then, you have to build an executable file. +>>|SHIELD:rtd-poc|<< -@example -$ ghdl -e hello_world -@end example +@tab -The @code{-e} option means @emph{elaborate}. With this option, @cite{GHDL} -creates code in order to elaborate a design, with the @code{hello_world} -entity at the top of the hierarchy. +PoC-Library@footnote{https://github.com/VLSI-EDA/PoC} -On GNU/Linux, if you have enabled the GCC backend during the compilation of @cite{GHDL}, -an executable program called @code{hello_world} which can be run is generated: +@tab -@example -$ ghdl -r hello_world -@end example +A Vendor-Independent, Open-Source IP Core and Utility Library. -or directly: +@item -@example -$ ./hello_world -@end example +>>|SHIELD:gh-vunit|<< -On Windows or if the GCC backend was not enabled, no file is created. -The simulation is launched using this command: +@tab -@example -> ghdl -r hello_world -@end example -The result of the simulation appears on the screen: -@example -Hello world! -@end example +@tab -@node A full adder,Starting with a design,The hello world program,Starting with GHDL -@anchor{Starting_with_GHDL a-full-adder}@anchor{a} -@section A full adder +VUnit@footnote{http://vunit.github.io/} +@tab -VHDL is generally used for hardware design. This example starts with -a full adder described in the @code{adder.vhdl} file: +A unit testing framework for VHDL/SystemVerilog -@example -entity adder is - -- `i0`, `i1` and the carry-in `ci` are inputs of the adder. - -- `s` is the sum output, `co` is the carry-out. - port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); -end adder; +@item -architecture rtl of adder is -begin - -- This full-adder architecture contains two concurrent assignment. - -- Compute the sum. - s <= i0 xor i1 xor ci; - -- Compute the carry. - co <= (i0 and i1) or (i0 and ci) or (i1 and ci); -end rtl; -@end example +>>|SHIELD:gl-p1076|<< -You can analyze this design file: +@tab -@example -$ ghdl -a adder.vhdl -@end example +>>|SHIELD:tw-p1076|<< -You can try to execute the @cite{adder} design, but this is useless, -since nothing externally visible will happen. In order to -check this full adder, a testbench has to be run. This testbench is -very simple, since the adder is also simple: it checks exhaustively all -inputs. Note that only the behaviour is tested, timing constraints are -not checked. The file @code{adder_tb.vhdl} contains the testbench for -the adder: +@tab -@example --- A testbench has no ports. -entity adder_tb is -end adder_tb; +IEEE P1076 WG@footnote{http://www.eda-twiki.org/vasg/} -architecture behav of adder_tb is - -- Declaration of the component that will be instantiated. - component adder - port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); - end component; +@tab - -- Specifies which entity is bound with the component. - for adder_0: adder use entity work.adder; - signal i0, i1, ci, s, co : bit; -begin - -- Component instantiation. - adder_0: adder port map (i0 => i0, i1 => i1, ci => ci, - s => s, co => co); +IEEE P1076 Working Group [VASG] - -- This process does the real job. - process - type pattern_type is record - -- The inputs of the adder. - i0, i1, ci : bit; - -- The expected outputs of the adder. - s, co : bit; - end record; - -- The patterns to apply. - type pattern_array is array (natural range <>) of pattern_type; - constant patterns : pattern_array := - (('0', '0', '0', '0', '0'), - ('0', '0', '1', '1', '0'), - ('0', '1', '0', '1', '0'), - ('0', '1', '1', '0', '1'), - ('1', '0', '0', '1', '0'), - ('1', '0', '1', '0', '1'), - ('1', '1', '0', '0', '1'), - ('1', '1', '1', '1', '1')); - begin - -- Check each pattern. - for i in patterns'range loop - -- Set the inputs. - i0 <= patterns(i).i0; - i1 <= patterns(i).i1; - ci <= patterns(i).ci; - -- Wait for the results. - wait for 1 ns; - -- Check the outputs. - assert s = patterns(i).s - report "bad sum value" severity error; - assert co = patterns(i).co - report "bad carry out value" severity error; - end loop; - assert false report "end of test" severity note; - -- Wait forever; this will finish the simulation. - wait; - end process; -end behav; -@end example +@end multitable -As usual, you should analyze the design: -@example -$ ghdl -a adder_tb.vhdl -@end example +@c # preload commonly known graphical characters like (c) -And build an executable for the testbench: +@c This data file has been placed in the public domain. -@example -$ ghdl -e adder_tb -@end example +@c Derived from the Unicode character mappings available from +@c . +@c Processed by unicode2rstsubs.py, part of Docutils: +@c . -You do not need to specify which object files are required: GHDL knows them -and automatically adds them in the executable. Now, it is time to run the -testbench: +@c # define a hard kine break for HTML -@example -$ ghdl -r adder_tb -adder_tb.vhdl:52:7:(assertion note): end of test -@end example +@c # This file provides the following shields: travis-ci appveyor release +@c # license mailing gitter issues-new issues-open issues-closed issues-pr +@c # issues-pr-closed github gh-logo -If your design is rather complex, you'd like to inspect signals. Signals -value can be dumped using the VCD file format. The resulting file can be -read with a wave viewer such as GTKWave. First, you should simulate your -design and dump a waveform file: +@c # Use http://b64.io/ to encode any image to base64. Then replace `/` with +@c # `%2F` and `+` with `%2B` (or use http://meyerweb.com/eric/tools/dencoder/). +@c # Beware that `?logo=data:image/png;base64,` must also be converted to +@c # percent encoding so that the URL is properly parsed. -@example -$ ghdl -r adder_tb --vcd=adder.vcd -@end example -Then, you may now view the waves: -@example -$ gtkwave adder.vcd -@end example -See @ref{b,,Simulation options}, for more details on the @ref{c,,--vcd} option and -other runtime options. +@node Contributing,Copyrights | Licenses,About GHDL,Top +@anchor{contribute contributing}@anchor{a}@anchor{contribute doc}@anchor{b}@anchor{contribute intro-contributing}@anchor{c} +@chapter Contributing -@node Starting with a design,,A full adder,Starting with GHDL -@anchor{Starting_with_GHDL starting-with-a-design}@anchor{d} -@section Starting with a design +The first step might be to use GHDL and explore it’s possibilities in an own project. If you are new to VHDL, see the +@ref{d,,Quick Start Guide} for an introduction. Furthermore, we encourage you to read @ref{e,,Invoking GHDL}, where the most +commonly used options are explained. You can also check the complete @ref{f,,Command Reference}. -Unless you are only studying VHDL, you will work with bigger designs than -the ones of the previous examples. +If you are more familiar with GHDL, you might start asking yourself how it works internally. Then, you might find +@ref{10,,Implementation of VHDL} and @ref{11,,Implementation of VITAL} interesting. -Let's see how to analyze and run a bigger design, such as the DLX model -suite written by Peter Ashenden which is distributed under the terms of the -GNU General Public License. A copy is kept on -@indicateurl{http://ghdl.free.fr/dlx.tar.gz} +While using GHDL, you might find flaws, such as bugs, missing features, typos in the documentation or topics which are +still not covered. In order to improve GHDL, we welcome bug reports, suggestions and contributions for any aspect of +GHDL. Either if it’s a bug or an enhancement, have a look at the and to see +if someone already told us about it. You might find a solution there. To get a broader view, you can also check the +Roadmap@footnote{http://poc-library.readthedocs.io/en/release/ChangeLog/index.html#change}. -First, untar the sources: +If you found no information on your topic, please, report so that we are aware! You can reach us through various ways: + or open a . -@example -$ tar zxvf dlx.tar.gz -@end example +@cartouche +@quotation Hint +Since the development of GHDL started fifteen years ago, multiple platforms have been used as a support for both distribution and getting feedback. However, the development is now centralized in >>|SHIELD:gh-logo|<<. +@end quotation +@end cartouche -In order not to pollute the sources with the library, it is a good idea -to create a @code{work/} subdirectory for the @cite{WORK} library. To -any GHDL commands, we will add the @code{--workdir=work} option, so -that all files generated by the compiler (except the executable) will be -placed in this directory. +@cartouche +@quotation Tip +How To Ask Questions The Smart Way@footnote{www.catb.org/~esr/faqs/smart-questions.html} +@end quotation +@end cartouche -@example -$ cd dlx -$ mkdir work -@end example +@menu +* Reporting bugs:: +* Requesting enhancements:: +* Improving the documentation:: +* Fork@comma{} modify and pull-request: Fork modify and pull-request. +* Related interesting projects:: -We will run the @code{dlx_test_behaviour} design. We need to analyze -all the design units for the design hierarchy, in the correct order. -GHDL provides an easy way to do this, by importing the sources: +@end menu -@example -$ ghdl -i --workdir=work *.vhdl -@end example +@node Reporting bugs,Requesting enhancements,,Contributing +@anchor{contribute reporting-bugs}@anchor{12}@anchor{contribute id1}@anchor{13} +@section Reporting bugs -and making a design: -@example -$ ghdl -m --workdir=work dlx_test_behaviour -@end example +@cartouche +@quotation Tip -Before this second stage, GHDL knows all the design units of the DLX, -but no one have been analyzed. The make command of GHDL analyzes and -elaborates a design. This creates many files in the @code{work/} -directory, and the @code{dlx_test_behaviour} executable in the current -directory. +@itemize * -The simulation needs to have a DLX program contained in the file -@code{dlx.out}. This memory image will be be loaded in the DLX memory. -Just take one sample: +@item +If the compiler crashes, this is a bug. Reliable tools never crash. -@example -$ cp test_loop.out dlx.out -@end example +@item +If the compiler emits an error message for a perfectly valid input or does not emit an error message for an invalid input, this may be a bug. -And you can run the test suite: +@item +If the executable created from your VHDL sources crashes, this may be a bug at runtime or the code itself may be wrong. However, since VHDL has a notion of pointers, an erroneous VHDL program (using invalid pointers for example) may crash. -@example -$ ghdl -r --workdir=work dlx_test_behaviour -@end example +@item +If a compiler message is not clear enough, please tell us. The error messages can be improved, but we have not enough experience with them. +@end itemize +@end quotation +@end cartouche -The test bench monitors the bus and displays each instruction executed. -It finishes with an assertion of severity level note: +Please, report issues of this kind through , as this allows us to categorize issues into groups and +assign developers to them. You can track the issue’s state and see how it’s getting solved. -@example -dlx-behaviour.vhdl:395:11:(assertion note): TRAP instruction - encountered, execution halted -@end example +@cartouche +@quotation Important +To make it easier, please elaborate a @cite{Minimum (non) Working Example} (MWE@footnote{https://en.wikipedia.org/wiki/Minimal_Working_Example}) prior to sending the report, so that the possible bug source is isolated. Shall the MWE compile and run, it is a good idea to make it look like a test and make an assert statement should finish the execution; the severity level @cite{note} indicates success, while a severity level @cite{failure} indicates failure. -Since the clock is still running, you have to manually stop the program -with the @code{C-c} key sequence. This behavior prevents you from running the -test bench in batch mode. However, you may force the simulator to -stop when an assertion above or equal a certain severity level occurs: +Then, please include enough information for the maintainers to reproduce the problem. This includes: -@example -$ ghdl -r --workdir=work dlx_test_behaviour --assert-level=note -@end example -With this option, the program stops just after the previous message: +@itemize * -@example -dlx-behaviour.vhdl:395:11:(assertion note): TRAP instruction - encountered, execution halted -error: assertion failed -@end example +@item +Operating system and version of GHDL (you can get it with @code{ghdl --version}). -If you want to make room on your hard drive, you can either: +@item +Whether you have built GHDL from sources (provide short SHA of the used commit) or used the binary distribution (tell which release/tag). @itemize * @item -clean the design library with the GHDL command: - -@example -$ ghdl --clean --workdir=work -@end example +If you cannot compile, please report which compiler you are using and the version. +@end itemize -This removes the executable and all the object files. If you want to -rebuild the design at this point, just do the make command as shown -above. +@item +Content of the input files which make the MWE @item -remove the design library with the GHDL command: +Description of the problem: -@example -$ ghdl --remove --workdir=work -@end example -This removes the executable, all the object files and the library file. -If you want to rebuild the design, you have to import the sources again, -and to make the design. +@itemize * @item -remove the @code{work/} directory: +Comment explaining whether the MWE should compile or not; if yes, whether or not is should run until the assertion. -@example -$ rm -rf work -@end example +@item +What you expected to happen and what you actually get. If you know the LRM well enough, please specify the paragraph which might be not well implemented. -Only the executable is kept. If you want to rebuild the design, create -the @code{work/} directory, import the sources, and make the design. -@end itemize +@item +Samples of any log. -Sometimes, a design does not fully follow the VHDL standards. For example it -uses the badly engineered @code{std_logic_unsigned} package. GHDL supports -this VHDL dialect through some options: +@item +Anything else that you think would be helpful. +@end itemize +@end itemize +@end quotation +@end cartouche -@example ---ieee=synopsys -fexplicit -@end example +@cartouche +@quotation Note +If you don’t know the LRM, be aware that an issue claimed as bug report may be rejected because there is no bug according to it. GHDL aims at implementing VHDL as defined in IEEE 1076@footnote{http://ieeexplore.ieee.org/document/4772740/}. However, some other tools allow constructs which do not fully follow the standard revisions. Therefore, comparisons with other VHDL is not a solid argument. Some of them are supported by GHDL (see @ref{14,,IEEE library pitfalls}), but any such enhancement will have very low priority. +@end quotation +@end cartouche -See @ref{e,,IEEE library pitfalls}, for more details. +@node Requesting enhancements,Improving the documentation,Reporting bugs,Contributing +@anchor{contribute requesting-enhancements}@anchor{15}@anchor{contribute id2}@anchor{16} +@section Requesting enhancements -@node Invoking GHDL,Simulation and runtime,Starting with GHDL,Top -@anchor{Invoking_GHDL invoking-ghdl}@anchor{f}@anchor{Invoking_GHDL doc}@anchor{10} -@chapter Invoking GHDL + -The form of the @code{ghdl} command is: +All enhancements and feature requests are welcome. Please open a new issue@footnote{https://github.com/tgingold/ghdl/issues/new} to report any, so you can track the request’s status and implementation. Depending on the complexity of the request, you may want to chat on Gitter@footnote{https://gitter.im/ghdl/ghdl1}, to polish it before opening an issue. -@example -ghdl command [options...] -@end example +@node Improving the documentation,Fork modify and pull-request,Requesting enhancements,Contributing +@anchor{contribute improving-the-documentation}@anchor{17} +@section Improving the documentation -The GHDL program has several commands. The first argument selects -the command. The options are used to slightly modify the action. -No option is allowed before the command. Except for the run command, -no option is allowed after a filename or a unit name. +If you found a mistake in the documentation, please send a comment. If you didn’t understand some parts of this manual, +please tell us. English is not our mother tongue, so this documentation may not be well-written. -If the number of options is large and the command line length is -beyond the system limit, you can use a response file. An argument that -starts with a @code{@@} is considered as a response file; it is replaced -by arguments read from the file (separated by blanks and end of line). +Likewise, rewriting part of the documentation or missing content (such as, examples) is a good way to improve it. Since +it automatically is built from @cite{reStructuredText} and @cite{Markdown} sources, you can fork, modify and request the +maintainers to pull your copy. See @ref{18,,Fork@comma{} modify and pull-request}. -@menu -* Building commands:: -* GHDL options:: -* Passing options to other programs:: -* GHDL Diagnostics Control:: -* GHDL warnings:: -* Rebuilding commands:: -* Library commands:: -* Cross-reference command:: -* File commands:: -* Misc commands:: -* VPI build commands:: -* Installation Directory:: -* IEEE library pitfalls:: -* IEEE math packages:: +@node Fork modify and pull-request,Related interesting projects,Improving the documentation,Contributing +@anchor{contribute pull-request}@anchor{18}@anchor{contribute fork-modify-and-pull-request}@anchor{19} +@section Fork, modify and pull-request -@end menu -@node Building commands,GHDL options,,Invoking GHDL -@anchor{Invoking_GHDL building-commands}@anchor{11} -@section Building commands +@cartouche +@quotation Tip +@itemize * -The mostly used commands of GHDL are those to analyze and elaborate a design. +@item +Before starting any modification, you might want to have a look at and , to check which other contributions are being made or have been made. If you observe that the modifications you are about to start might conflict with any other, please or open a to coordinate. -@menu -* Analysis command:: -* Elaboration command:: -* Run command:: -* Elaborate and run command:: -* Bind command:: -* Link command:: -* List link command:: -* Check syntax command:: -* Analyze and elaborate command:: +@item +See section @ref{1a,,Directory Structure} to faster find the location of the sources you need to modify, and/or to know where to place new ones. +@end itemize +@end quotation +@end cartouche -@end menu +Contributing source code/documentation via Git@footnote{https://git-scm.com/} is very easy. Although we don’t provide direct +write access to our repositories, the project is hosted at GitHub, which follows a fork, edit and pull-request +flow@footnote{https://help.github.com/articles/github-flow/} . That is: -@node Analysis command,Elaboration command,,Building commands -@anchor{Invoking_GHDL analysis-command}@anchor{12} -@subsection Analysis command +@enumerate -@geindex analysis +@item +Make a copy (fork@footnote{https://help.github.com/articles/fork-a-repo/}) of the project. -@geindex -a command +@item +Do the changes you wish (edit, add, rename, move and/or delete). -Analyze one or several files: +@item +When you think that the changes are ready to be merged, you notify the maintainers by opening a Pull Request@footnote{https://help.github.com/articles/creating-a-pull-request/} (PR). -@example -ghdl -a [options...] file... -@end example +@item +The maintainers will review the proposed changes and will reply in the corresponding thread if any further modification is required. If so, you can keep adding commits to the same branch, and the PR will be automatically updated. -The analysis command compiles one or more files, and creates an -object file for each source file. The analysis command is selected with -@code{-a} switch. Any argument starting with a dash is an option, the -others are filenames. No options are allowed after a filename -argument. GHDL analyzes each filename in the given order, and stops the -analysis in case of error (the following files are not analyzed). +@item +Last, the maintainers will merge your branch. You will be notified, the PR will be closed, and you’ll be allowed to delete the branch, if you want. +@end enumerate -See @ref{13,,GHDL options}, for details on the GHDL options. For example, -to produce debugging information such as line numbers, use: +@cartouche +@quotation Tip -@example -ghdl -a -g my_design.vhdl -@end example +@itemize * -@node Elaboration command,Run command,Analysis command,Building commands -@anchor{Invoking_GHDL id1}@anchor{14}@anchor{Invoking_GHDL elaboration-command}@anchor{15} -@subsection Elaboration command +@item +It is recommended to read A successful Git branching model@footnote{http://nvie.com/posts/a-successful-git-branching-model/} for a reference on how maintainers expect to handle multiple branches. However, our actual model is not as exhaustive as explained there. +@item +Some commit messages can automatically close@footnote{https://help.github.com/articles/closing-issues-via-commit-messages/} issues. This is a very useful feature, which you are not required to use. However beware that using @cite{fix} anywhere in the commit message can have side effects. If you closed any issue unexpectedly, just reply to it (even if it’s closed) so that maintainers can check it. +@end itemize +@end quotation +@end cartouche -@geindex elaboration +@node Related interesting projects,,Fork modify and pull-request,Contributing +@anchor{contribute related-interesting-projects}@anchor{1b} +@section Related interesting projects -@geindex -e command -Elaborate a design: +If you have an interesting project, please send us feedback or get listed on our @ref{8,,Who uses GHDL?} page. -@example -ghdl -e [options..] primary_unit [secondary_unit] -@end example +@c # preload commonly known graphical characters like (c) -On GNU/Linux, if the GCC backend was enabled during the compilation of @cite{GHDL}, -the elaboration command creates an executable containing the code of the @cite{VHDL} -sources, the elaboration code and simulation code to execute a design -hierarchy. The executable is created in the current directory. -On Windows or if the GCC backend was not enabled, this command elaborates the design -but does not generate anything. +@c This data file has been placed in the public domain. -The elaboration command is selected with @code{-e} switch, and must be -followed by either: +@c Derived from the Unicode character mappings available from +@c . +@c Processed by unicode2rstsubs.py, part of Docutils: +@c . +@c # define a hard kine break for HTML -@itemize * +@c # This file provides the following shields: travis-ci appveyor release +@c # license mailing gitter issues-new issues-open issues-closed issues-pr +@c # issues-pr-closed github gh-logo -@item -a name of a configuration unit +@c # Use http://b64.io/ to encode any image to base64. Then replace `/` with +@c # `%2F` and `+` with `%2B` (or use http://meyerweb.com/eric/tools/dencoder/). +@c # Beware that `?logo=data:image/png;base64,` must also be converted to +@c # percent encoding so that the URL is properly parsed. -@item -a name of an entity unit -@item -a name of an entity unit followed by a name of an architecture unit -@end itemize -Name of the units must be a simple name, without any dot. You can -select the name of the @cite{WORK} library with the @code{--work=NAME} -option, as described in @ref{13,,GHDL options}. -See @ref{16,,Top entity}, for the restrictions on the root design of a -hierarchy. +@node Copyrights | Licenses,Quick Start Guide,Contributing,Top +@anchor{licenses copyrights-licenses}@anchor{1c}@anchor{licenses doc}@anchor{1d}@anchor{licenses intro-copyrights}@anchor{1e} +@chapter Copyrights | Licenses -On GNU/Linux the filename of the executable is the name of the -primary unit, or for the later case, the concatenation of the name of -the primary unit, a dash, and the name of the secondary unit (or -architecture). On Windows there is no executable generated. -The @code{-o} followed by a filename can override the default -executable filename. -For the elaboration command, @cite{GHDL} re-analyzes all the -configurations, entities, architectures and package declarations, and -creates the default configurations and the default binding indications -according to the LRM rules. It also generates the list of objects files -required for the executable. Then, it links all these files with the -runtime library. +@itemize - -The actual elaboration is performed at runtime. +@item +The GHDL front-end, package @code{std.textio} and the runtime library, @code{grt}, are given under @ref{1f,,GNU GPLv2}. -On Windows this command can be skipped because it is also done by the -run command. +@item +The documentation is given under @ref{20,,CC-BY-SA}. +@end itemize -@node Run command,Elaborate and run command,Elaboration command,Building commands -@anchor{Invoking_GHDL run-command}@anchor{17}@anchor{Invoking_GHDL id2}@anchor{18} -@subsection Run command +@cartouche +@quotation Warning +As a consequence of the runtime copyright, you are not allowed to distribute an executable produced by GHDL without the VHDL sources. To my mind, this is not a real restriction, since it is pointless to distribute VHDL executable. Please, send a comment (@ref{15,,Requesting enhancements}) if you don’t like this policy. +@end quotation +@end cartouche -@geindex run +@itemize - -@geindex -r command +@item +The following packages are copyrighted by third parties (see corresponding sources for more information): -Run (or simulate) a design: +@quotation -@example -ghdl -r [options...] primary_unit [secondary_unit] [simulation_options...] -@end example -The options and arguments are the same as for the elaboration command, @ref{15,,Elaboration command}. +@itemize - -On GNU/Linux this command simply determines the filename of the executable -and executes it. Options are ignored. You may also directly execute -the program. The executable must be in the current directory. +@item +These from library @code{ieee} are copyrighted by Institute of Electrical and Electronics Engineers (IEEE)@footnote{https://www.ieee.org} : -This command exists for three reasons: +@quotation -@itemize * +@itemize - @item -You don't have to create the executable program name. +@code{numeric_bit} and @code{numeric_std}: the source files may be distributed without change, except as permitted by the standard; these may not be sold or distributed for profit. [see also IEEE 1076.3@footnote{http://ieeexplore.ieee.org/document/592543/} ] @item -It is coherent with the @code{-a} and @code{-e} commands. +@code{std_logic_1164}, @code{Math_Real} and @code{Math_Complex} @item -It works with the Windows implementation, where the code is generated in -memory. +@code{VITAL_Primitives}, @code{VITAL_Timing} and @code{VITAL_Memory} [see also IEEE 1076.4@footnote{http://ieeexplore.ieee.org/document/954750/} ] @end itemize +@end quotation -On Windows this command elaborates and launches the simulation. As a consequence -you must use the same options used during analysis. - -See @ref{19,,Simulation and runtime}, for details on options. - -@node Elaborate and run command,Bind command,Run command,Building commands -@anchor{Invoking_GHDL elaborate-and-run-command}@anchor{1a} -@subsection Elaborate and run command - - -@geindex elaborate and run - -@geindex --elab-run command +@item +The following sources may be used and distributed without restriction, provided that the copyright statements are not removed from the files and that any derivative work contains the copyright notice. -Elaborate and then simulate a design unit: +@quotation -@example -ghdl --elab-run [elab_options...] primary_unit [secondary_unit] [run_options...] -@end example -This command acts like the elaboration command (see @ref{15,,Elaboration command}) -followed by the run command (see @ref{17,,Run command}). +@itemize - -@node Bind command,Link command,Elaborate and run command,Building commands -@anchor{Invoking_GHDL bind-command}@anchor{1b}@anchor{Invoking_GHDL id3}@anchor{1c} -@subsection Bind command +@item +@code{synopsys} directory: @code{std_logic_arith}, @code{std_logic_signed}, @code{std_logic_unsigned} and @code{std_logic_textio} are copyrighted by Synopsys@comma{} Inc.@footnote{https://www.synopsys.com/} +@item +@code{mentor} directory: @code{std_logic_arith} is copyrighted by Mentor Graphics@footnote{https://www.mentor.com} +@end itemize +@end quotation +@end itemize +@end quotation +@end itemize -@geindex binding +@menu +* GNU GPLv2:: +* CC-BY-SA:: +* List of Contributors:: -@geindex --bind command +@end menu -Bind a design unit and prepare the link step: +@node GNU GPLv2,CC-BY-SA,,Copyrights | Licenses +@anchor{licenses lic-gplv2}@anchor{1f}@anchor{licenses gnu-gplv2}@anchor{21} +@section GNU GPLv2 -@example -ghdl --bind [options] primary_unit [secondary_unit] -@end example -This command is only available on GNU/Linux. +GHDL is copyright © 2002 - 2017 Tristan Gingold. -This performs only the first stage of the elaboration command; the list -of objects files is created but the executable is not built. This -command should be used only when the main entry point is not ghdl. +This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. -@node Link command,List link command,Bind command,Building commands -@anchor{Invoking_GHDL link-command}@anchor{1d}@anchor{Invoking_GHDL id4}@anchor{1e} -@subsection Link command +This program is distributed in the hope that it will be useful, but @strong{WITHOUT ANY WARRANTY}; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License@footnote{https://www.gnu.org/licenses/old-licenses/gpl-2.0.html} for more details. +@node CC-BY-SA,List of Contributors,GNU GPLv2,Copyrights | Licenses +@anchor{licenses lic-cc-by-sa}@anchor{20}@anchor{licenses cc-by-sa}@anchor{22} +@section CC-BY-SA -@geindex linking -@geindex --link command +This is a free documentation; you can redistribute it and/or modify it under the terms of the Creative Commons Attribution-ShareAlike 4.0@footnote{https://creativecommons.org/licenses/by-sa/4.0/} license. You are free to @strong{share} (copy and redistribute the material in any medium or format) and/or @strong{adapt} (remix, transform, and build upon the material for any purpose, even commercially). We cannot revoke these freedoms as long as you follow the these terms: -Link an already bound design unit: -@example -ghdl --link [options] primary_unit [secondary_unit] -@end example +@itemize - -This performs only the second stage of the elaboration command: the -executable is created by linking the files of the object files list. -This command is available only for completeness. The elaboration command is -equivalent to the bind command followed by the link command. +@item +@strong{Attribution}: you must provide the name of the creator and attribution parties (more info@footnote{https://wiki.creativecommons.org/wiki/License_Versions#Detailed_attribution_comparison_chart}), a copyright notice, a license notice, a disclaimer notice, a link to the material, a link to the license and indicate if changes were made (see marking guide@footnote{https://wiki.creativecommons.org/wiki/Best_practices_for_attribution#This_is_a_good_attribution_for_material_you_modified_slightly} and more info@footnote{https://wiki.creativecommons.org/wiki/License_Versions#Modifications_and_adaptations_must_be_marked_as_such} ). You may do so in any reasonable manner, but not in any way that suggests we endorses you or your use. -@node List link command,Check syntax command,Link command,Building commands -@anchor{Invoking_GHDL list-link-command}@anchor{1f}@anchor{Invoking_GHDL id5}@anchor{20} -@subsection List link command +@item +@strong{ShareAlike}: if you remix, transform, or build upon the material, you must distribute your contributions under the same license as the original. +@item +No additional restrictions: you may not apply legal terms or technological measures that legally restrict others from doing anything the license permits. +@end itemize -@geindex --list-link command +See CC-BY-SA-4.0 Legal Code@footnote{https://creativecommons.org/licenses/by-sa/4.0/legalcode.txt} for more details. -Display files which will be linked: +@node List of Contributors,,CC-BY-SA,Copyrights | Licenses +@anchor{licenses lic-contributors}@anchor{23}@anchor{licenses list-of-contributors}@anchor{24} +@section List of Contributors -@example -ghdl --list-link primary_unit [secondary_unit] -@end example -This command is only available on GNU/Linux. -This command may be used only after a bind command. GHDL displays all -the files which will be linked to create an executable. This command is -intended to add object files in a link of a foreign program. +@multitable {xxxxxxxxxxxxxxxxxxxxxxxxxxx} {xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx} +@headitem -@node Check syntax command,Analyze and elaborate command,List link command,Building commands -@anchor{Invoking_GHDL id6}@anchor{21}@anchor{Invoking_GHDL check-syntax-command}@anchor{22} -@subsection Check syntax command +Contributor @footnote{ +In alphabetical order. +} +@tab -@geindex checking syntax +Role -@geindex -s command +@item -Analyze files but do not generate code: +Baggett, Jonas -@example -ghdl -s [options] files -@end example +@tab -This command may be used to check the syntax of files. It does not update -the library. +signal selection -@node Analyze and elaborate command,,Check syntax command,Building commands -@anchor{Invoking_GHDL analyze-and-elaborate-command}@anchor{23}@anchor{Invoking_GHDL id7}@anchor{24} -@subsection Analyze and elaborate command +@item +Bertram, Felix -@geindex Analyze and elaborate command +@tab -@geindex -c command +VPI interface -Analyze files and elaborate them at the same time. +@item -On GNU/Linux: +Davis, Brian -@example -ghdl -c [options] file... -e primary_unit [secondary_unit] -@end example +@tab -On Windows: +Windows Mcode builds -@example -ghdl -c [options] file... -r primary_unit [secondary_unit] -@end example +@item -This command combines analysis and elaboration: files are analyzed and -the unit is then elaborated. However, code is only generated during the -elaboration. On Windows the simulation is launched. +Drummond, Brian -To be more precise, the files are first parsed, and then the elaboration -drives the analysis. Therefore, there is no analysis order, and you don't -need to care about it. +@tab -All the units of the files are put into the @cite{work} library. But, the -work library is neither read from disk nor saved. Therefore, you must give -all the files of the @cite{work} library your design needs. +GCC 4.8.2 update, OSVVM port, some bugfixes -The advantages over the traditional approach (analyze and then elaborate) are: +@item +Gingold, Tristan @footnote{ +Maintainer. +} -@itemize * +@tab -@item -The compilation cycle is achieved in one command. +@strong{Sole author of GHDL as a whole} -@item -Since the files are only parsed once, the compilation cycle may be faster. +@item -@item -You don't need to know an analysis order +Jensen, Adam -@item -This command produces smaller executable, since unused units and subprograms -do not generate code. -@end itemize +@tab -However, you should know that currently most of the time is spent in code -generation and the analyze and elaborate command generate code for all units -needed, even units of @code{std} and @code{ieee} libraries. Therefore, -according to the design, the time for this command may be higher than the time -for the analyze command followed by the elaborate command. +FreeBSD builds -This command is still experimental. In case of problems, you should go back -to the traditional way. +@item -@node GHDL options,Passing options to other programs,Building commands,Invoking GHDL -@anchor{Invoking_GHDL ghdl-options}@anchor{13}@anchor{Invoking_GHDL id8}@anchor{25} -@section GHDL options +Koch, Markus +@tab -@geindex IEEE 1164 +vendor pre-compile script for Lattice (GNU/Linux) -@geindex 1164 +@item -@geindex IEEE 1076.3 +Koontz, David -@geindex 1076.3 +@tab -Besides the options described below, @cite{GHDL} passes any debugging options -(those that begin with @code{-g}) and optimizations options (those that -begin with @code{-O} or @code{-f}) to @cite{GCC}. Refer to the @cite{GCC} -manual for details. +Mac OSX builds, LRM compliance work, bugfix analyses -@c option::--work= -@c -@c .. index:: WORK library -@c -@c Specify the name of the :samp:`WORK` library. Analyzed units are always -@c placed in the library logically named :samp:`WORK`. With this option, -@c you can set its name. By default, the name is :samp:`work`. -@c -@c `GHDL` checks whether :samp:`WORK` is a valid identifier. Although being -@c more or less supported, the :samp:`WORK` identifier should not be an -@c extended identifier, since the filesystem may prevent it from correctly -@c working (due to case sensitivity or forbidden characters in filenames). -@c -@c `VHDL` rules forbid you to add units to the :samp:`std` library. -@c Furthermore, you should not put units in the :samp:`ieee` library. +@item -@geindex command line option; --workdir= -@anchor{Invoking_GHDL cmdoption--workdir}@anchor{26} -@deffn {Option} @w{-}@w{-}workdir= +Lehmann, Patrick -Specify the directory where the @code{WORK} library is located. When this -option is not present, the @code{WORK} library is in the current -directory. The object files created by the compiler are always placed -in the same directory as the @code{WORK} library. +@tab -Use option @ref{27,,-P} to specify where libraries other than @code{WORK} -are placed. -@end deffn +Windows compile scripts, vendor library pre-compile scripts (win+lin), building in MinGW, AppVeyor integration. -@geindex command line option; --std= -@anchor{Invoking_GHDL cmdoption--std}@anchor{28} -@deffn {Option} @w{-}@w{-}std= +@item -Specify the standard to use. By default, the standard is @code{93c}, which -means VHDL-93 accepting VHDL-87 syntax. For details on @code{STD} values see -@ref{29,,VHDL standards}. -@end deffn +Martinez-Corral, Unai -@geindex command line option; --ieee= -@anchor{Invoking_GHDL cmdoption--ieee}@anchor{2a} -@deffn {Option} @w{-}@w{-}ieee= +@tab -@geindex ieee library +Docker builds, Travis-CI & Docker, adapt/fix RTD theme -@geindex synopsys library +@item -@geindex mentor library +van Rantwijk, Joris -Select the @code{IEEE} library to use. @code{VER} must be one of: +@tab +Debian packaging -@table @asis +@end multitable -@item none -Do not supply an @cite{IEEE} library. Any library clause with the @code{IEEE} -identifier will fail, unless you have created by your own a library with -the @cite{IEEE} name. +Only those who made substantial contributions are shown in the table above, but many others contributed with minor patches. You can find a list at -@item standard +With apologies to anyone who ought to be either on this table or in the GitHub contributor list, but isn’t. Thanks also to all those who have reported bugs and support issues, and often patches and testcases to either the late gna! website or sourceforge.net/p/ghdl-updates/tickets@footnote{https://sourceforge.net/p/ghdl-updates/tickets/} . -Supply an @cite{IEEE} library containing only packages defined by -@code{ieee} standards. Currently, there are the multivalue logic system -packages @code{std_logic_1164} defined by IEEE 1164, the synthesis -packages , @code{numeric_bit} and @code{numeric_std} defined by IEEE -1076.3, and the @code{vital} packages @code{vital_timing} and -@code{vital_primitives}, defined by IEEE 1076.4. The version of these -packages is defined by the VHDL standard used. See @ref{2b,,VITAL packages}, -for more details. -@item synopsys +__________________________________________________________________ -Supply the former packages and the following additional packages: -@code{std_logic_arith}, @code{std_logic_signed}, -@code{std_logic_unsigned}, @code{std_logic_textio}. -These packages were created by some companies, and are popular. However -they are not standard packages, and have been placed in the @cite{IEEE} -library without the permission from the @code{ieee}. +@c # preload commonly known graphical characters like (c) -@item mentor +@c This data file has been placed in the public domain. -Supply the standard packages and the following additional package: -@code{std_logic_arith}. The package is a slight variation of a definitely -not standard but widely mis-used package. -@end table +@c Derived from the Unicode character mappings available from +@c . +@c Processed by unicode2rstsubs.py, part of Docutils: +@c . -To avoid errors, you must use the same @cite{IEEE} library for all units of -your design, and during elaboration. -@end deffn +@c # define a hard kine break for HTML -@geindex command line option; -P -@anchor{Invoking_GHDL cmdoption-P}@anchor{27} -@deffn {Option} @w{-}P +@node Quick Start Guide,Invoking GHDL,Copyrights | Licenses,Top +@anchor{using/QuickStartGuide quick-start-guide}@anchor{25}@anchor{using/QuickStartGuide using-quickstart}@anchor{d}@anchor{using/QuickStartGuide doc}@anchor{26} +@chapter Quick Start Guide -Add @cite{DIRECTORY} to the end of the list of directories to be searched for -library files. A library is searched in @cite{DIRECTORY} and also in -@cite{DIRECTORY/LIB/vVV} (where @cite{LIB} is the name of the library and @cite{VV} -the vhdl standard). -The @cite{WORK} library is always searched in the path specified by the -@code{--workdir=} option, or in the current directory if the latter -option is not specified. -@end deffn +In this chapter, you will learn how to use @cite{GHDL} by working on a few examples. -@geindex command line option; -fexplicit -@anchor{Invoking_GHDL cmdoption-fexplicit}@anchor{2c} -@deffn {Option} @w{-}fexplicit +@menu +* The ‘Hello world’ program:: +* The heartbeat program:: +* A full adder:: +* Starting with a design:: -When two operators are overloaded, give preference to the explicit declaration. -This may be used to avoid the most common pitfall of the @code{std_logic_arith} -package. See @ref{e,,IEEE library pitfalls}, for an example. +@end menu -This option is not set by default. I don't think this option is a -good feature, because it breaks the encapsulation rule. When set, an -operator can be silently overridden in another package. You'd better to fix -your design and use the @code{numeric_std} package. -@end deffn +@node The ‘Hello world’ program,The heartbeat program,,Quick Start Guide +@anchor{using/QuickStartGuide the-hello-world-program}@anchor{27} +@section The @cite{‘Hello world’} program -@geindex command line option; -frelaxed-rules -@anchor{Invoking_GHDL cmdoption-frelaxed-rules}@anchor{2d} -@deffn {Option} @w{-}frelaxed@w{-}rules -Within an object declaration, allow to reference the name (which -references the hidden declaration). This ignores the error in the -following code: +To illustrate the large purpose of @cite{VHDL}, here is a commented @cite{‘Hello world’} program which saved in a file named @code{hello.vhdl}: @example -package pkg1 is - type state is (state1, state2, state3); -end pkg1; - -use work.pkg1.all; -package pkg2 is - constant state1 : state := state1; -end pkg2; -@end example +-- Hello world program. +use std.textio.all; -- Imports the standard textio package. -Some code (such as Xilinx packages) have such constructs, which -are valid. +-- Defines a design entity, without any ports. +entity hello_world is +end hello_world; -(The scope of the @code{state1} constant start at the @cite{constant} -word. Because the constant @code{state1} and the enumeration literal -@code{state1} are homograph, the enumeration literal is hidden in the -immediate scope of the constant). +architecture behaviour of hello_world is +begin + process + variable l : line; + begin + write (l, String'("Hello world!")); + writeline (output, l); + wait; + end process; +end behaviour; +@end example -This option also relaxes the rules about pure functions. Violations -result in warnings instead of errors. -@end deffn +@cartouche +@quotation Tip -@geindex command line option; -fpsl -@anchor{Invoking_GHDL cmdoption-fpsl}@anchor{2e} -@deffn {Option} @w{-}fpsl +@itemize * -Enable parsing of PSL assertions within comments. See @ref{2f,,PSL implementation}, -for more details. -@end deffn +@item +Both @code{.vhdl} and @code{.vhd} extensions are used for VHDL source files, while @code{.v} is used for Verilog. -@geindex command line option; --no-vital-checks -@anchor{Invoking_GHDL cmdoption--no-vital-checks}@anchor{30} -@deffn {Option} @w{-}@w{-}no@w{-}vital@w{-}checks -@end deffn +@item +Unless you use especial characters, either @cite{UTF-8} or @cite{ISO-8859-1} encodings can be used. However, if you do, the latter should be used. The standard defines ASCII (7-bit encoding) or ISO Latin-1 (ISO-8859-1) as default. However, GHDL has a relaxing option, @ref{28,,--mb-comments} (multi byte), to allow UTF-8 or other encodings in comments. +@end itemize +@end quotation +@end cartouche -@geindex command line option; --vital-checks -@anchor{Invoking_GHDL cmdoption--vital-checks}@anchor{31} -@deffn {Option} @w{-}@w{-}vital@w{-}checks -Disable or enable checks of restriction on VITAL units. Checks are enabled -by default. +@itemize - -Checks are performed only when a design unit is decorated by a VITAL attribute. -The VITAL attributes are @code{VITAL_Level0} and @code{VITAL_Level1}, both -declared in the @code{ieee.VITAL_Timing} package. +@item +First, you have to compile the file; this is called @cite{analysis} of a design file in @cite{VHDL} terms. Run @code{ghdl -a hello.vhdl} in the @cite{shell}. This command creates or updates a file @code{work-obj93.cf}, which describes the library @code{work}. -Currently, VITAL checks are only partially implemented. See -@ref{32,,VHDL restrictions for VITAL}, for more details. -@end deffn +@item +Then, run @code{ghdl -e hello_world} in the @cite{shell}. Option @ref{29,,-e} means @emph{elaborate}, which is used to build a design, with the @code{hello_world} entity at the top of the hierarchy. -@geindex command line option; --syn-binding -@anchor{Invoking_GHDL cmdoption--syn-binding}@anchor{33} -@deffn {Option} @w{-}@w{-}syn@w{-}binding +@item +Last, you can directly launch the simulation running @code{ghdl -r hello_world} in the @cite{shell}. The result of the simulation will be shown on screen: +@end itemize -Use synthesizer rules for component binding. During elaboration, if a -component is not bound to an entity using VHDL LRM rules, try to find -in any known library an entity whose name is the same as the component -name. +@example +Hello world! +@end example -This rule is known as synthesizer rule. +@cartouche +@quotation Hint +If a GCC/LLVM variant of @cite{GHDL} is used: -There are two key points: normal VHDL LRM rules are tried first and -entities are searched only in known library. A known library is a -library which has been named in your design. -This option is only useful during elaboration. -@end deffn +@itemize * -@geindex command line option; --PREFIX= -@anchor{Invoking_GHDL cmdoption--PREFIX}@anchor{34} -@deffn {Option} @w{-}@w{-}PREFIX= +@item +@cite{Analysis} generates a file, @code{hello.o}, which is the object file corresponding to your @cite{VHDL} program. This is not created with mcode. -Use @code{PATH} as the prefix path to find commands and pre-installed (std and -ieee) libraries. -@end deffn +@item +The elaboration step is compulsory after the analysis and prior to launching the simulation; This wil generate an executable binary named @code{hello_world}. -@geindex command line option; --GHDL1= -@anchor{Invoking_GHDL cmdoption--GHDL1}@anchor{35} -@deffn {Option} @w{-}@w{-}GHDL1= +@item +As a result, @ref{2a,,-r} is just a passthrough to the binary generated in the @cite{elaboration}. Therefore, the executable can be run directly, @code{./hello_world}. See @ref{2a,,-r} for more informartion. +@end itemize +@end quotation +@end cartouche -Use @code{COMMAND} as the command name for the compiler. If @code{COMMAND} is -not a path, then it is searched in the path. -@end deffn +@cartouche +@quotation Hint +@ref{29,,-e} can be bypassed with mcode, since @ref{2a,,-r} actually elaborates the design and saves it on memory before running the simulation. But you can still use it to check for some elaboration problems. +@end quotation +@end cartouche -@geindex command line option; --AS= -@anchor{Invoking_GHDL cmdoption--AS}@anchor{36} -@deffn {Option} @w{-}@w{-}AS= +@node The heartbeat program,A full adder,The ‘Hello world’ program,Quick Start Guide +@anchor{using/QuickStartGuide the-heartbeat-program}@anchor{2b} +@section The @cite{heartbeat} program -Use @code{COMMAND} as the command name for the assembler. If @code{COMMAND} is -not a path, then it is searched in the path. The default is @code{as}. -@end deffn -@geindex command line option; --LINK= -@anchor{Invoking_GHDL cmdoption--LINK}@anchor{37} -@deffn {Option} @w{-}@w{-}LINK= +@example +entity hello_world is + port ( clk: out std_logic; ) +end hearbeat; -Use @code{COMMAND} as the linker driver. If @code{COMMAND} is -not a path, then it is searched in the path. The default is @code{gcc}. -@end deffn +architecture behaviour of hello_world is +begin + -- Clock process definition + clk_process: process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; +end behaviour; +@end example -@geindex command line option; -v -@anchor{Invoking_GHDL cmdoption-v}@anchor{38} -@deffn {Option} @w{-}v +@node A full adder,Starting with a design,The heartbeat program,Quick Start Guide +@anchor{using/QuickStartGuide a-full-adder}@anchor{2c} +@section A full adder -Be verbose. For example, for analysis, elaboration and make commands, GHDL -displays the commands executed. -@end deffn -@node Passing options to other programs,GHDL Diagnostics Control,GHDL options,Invoking GHDL -@anchor{Invoking_GHDL passing-options-to-other-programs}@anchor{39} -@section Passing options to other programs +VHDL is generally used for hardware design. This example starts with a full adder@footnote{https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder} described in a file named @code{adder.vhdl}: +@example +entity adder is + -- `i0`, `i1` and the carry-in `ci` are inputs of the adder. + -- `s` is the sum output, `co` is the carry-out. + port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); +end adder; -These options are only available on GNU/Linux. - -For many commands, @cite{GHDL} acts as a driver: it invokes programs to perform -the command. You can pass arbitrary options to these programs. +architecture rtl of adder is +begin + -- This full-adder architecture contains two concurrent assignment. + -- Compute the sum. + s <= i0 xor i1 xor ci; + -- Compute the carry. + co <= (i0 and i1) or (i0 and ci) or (i1 and ci); +end rtl; +@end example -Both the compiler and the linker are in fact GCC programs. See the -GCC manual for details on GCC options. +You can analyze this design file, @code{ghdl -a adder.vhdl}, and try to execute the @cite{adder} design. But this is useless, since nothing externally visible will happen. In order to check this full adder, a @emph{testbench} has to be run. This testbench is very simple, since the adder is also simple: it checks exhaustively all inputs. Note that only the behaviour is tested, timing constraints are not checked. A file named @code{adder_tb.vhdl} contains the testbench for the adder: -@geindex command line option; -Wc@comma{}