From 108c48221f7a367b2b33499b469eab0afcaafd43 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 30 Sep 2019 01:13:08 +0200
Subject: testsuite/synth: add testcase for #948

---
 testsuite/synth/aggr01/aggr02.vhdl    |  1 -
 testsuite/synth/issue948/ent.vhdl     | 22 ++++++++++++++++++++++
 testsuite/synth/issue948/testsuite.sh | 11 +++++++++++
 3 files changed, 33 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/issue948/ent.vhdl
 create mode 100755 testsuite/synth/issue948/testsuite.sh

diff --git a/testsuite/synth/aggr01/aggr02.vhdl b/testsuite/synth/aggr01/aggr02.vhdl
index 82e83ff9c..8b117867b 100644
--- a/testsuite/synth/aggr01/aggr02.vhdl
+++ b/testsuite/synth/aggr01/aggr02.vhdl
@@ -17,4 +17,3 @@ architecture behav of aggr02 is
 begin
   b <= a and gen_mask (8);
 end behav;
-    
diff --git a/testsuite/synth/issue948/ent.vhdl b/testsuite/synth/issue948/ent.vhdl
new file mode 100644
index 000000000..a2f7aadb9
--- /dev/null
+++ b/testsuite/synth/issue948/ent.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+        i : in bit;
+        o : out bit
+    );
+end;
+
+architecture a of ent is
+    signal test : std_logic_vector(7 downto 0);
+    alias a : std_logic_vector(7 downto 0) is test;
+begin
+    process(i)
+    begin
+        if a = x"00" then
+        end if;
+
+        o <= i;
+    end process;
+end;
diff --git a/testsuite/synth/issue948/testsuite.sh b/testsuite/synth/issue948/testsuite.sh
new file mode 100755
index 000000000..54e687d28
--- /dev/null
+++ b/testsuite/synth/issue948/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for f in ent; do
+  synth $f.vhdl -e $f > syn_$f.vhdl
+#  analyze syn_$f.vhdl
+done
+clean
+
+echo "Test successful"
-- 
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