From 0edaa61d52fff06dda6e582c4ffe5af6d970a190 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 5 Mar 2023 09:24:15 +0100
Subject: testsuite/synth: add a test for #2372

---
 testsuite/synth/issue2372/testsuite.sh | 8 ++++++++
 testsuite/synth/issue2372/to01.vhdl    | 7 +++++++
 2 files changed, 15 insertions(+)
 create mode 100755 testsuite/synth/issue2372/testsuite.sh
 create mode 100644 testsuite/synth/issue2372/to01.vhdl

diff --git a/testsuite/synth/issue2372/testsuite.sh b/testsuite/synth/issue2372/testsuite.sh
new file mode 100755
index 000000000..ccb2ebf27
--- /dev/null
+++ b/testsuite/synth/issue2372/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only to01
+
+echo "Test successful"
diff --git a/testsuite/synth/issue2372/to01.vhdl b/testsuite/synth/issue2372/to01.vhdl
new file mode 100644
index 000000000..e54c74808
--- /dev/null
+++ b/testsuite/synth/issue2372/to01.vhdl
@@ -0,0 +1,7 @@
+library IEEE; use IEEE.std_logic_1164.all;
+entity to01 is 
+  port (din : in std_logic; dout : out std_logic);
+end;
+architecture test of to01 is begin
+  dout <= to_01(din);
+end;
-- 
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