From 0401816b5cbe3c153bb358b8d2ed92f3cde60fa4 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 6 Dec 2020 08:43:20 +0100
Subject: testsuite/synth: add a testcase for #1531

---
 testsuite/synth/issue1531/sgn.vhdl     | 20 ++++++++++++++++++++
 testsuite/synth/issue1531/tb_sgn.vhdl  | 23 +++++++++++++++++++++++
 testsuite/synth/issue1531/tb_uns.vhdl  | 23 +++++++++++++++++++++++
 testsuite/synth/issue1531/testsuite.sh |  8 ++++++++
 testsuite/synth/issue1531/uns.vhdl     | 20 ++++++++++++++++++++
 5 files changed, 94 insertions(+)
 create mode 100644 testsuite/synth/issue1531/sgn.vhdl
 create mode 100644 testsuite/synth/issue1531/tb_sgn.vhdl
 create mode 100644 testsuite/synth/issue1531/tb_uns.vhdl
 create mode 100755 testsuite/synth/issue1531/testsuite.sh
 create mode 100644 testsuite/synth/issue1531/uns.vhdl

diff --git a/testsuite/synth/issue1531/sgn.vhdl b/testsuite/synth/issue1531/sgn.vhdl
new file mode 100644
index 000000000..cb1767184
--- /dev/null
+++ b/testsuite/synth/issue1531/sgn.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sgn is
+  port (
+    o1 : out std_logic_vector(1 downto 0);
+    o2 : out std_logic_vector (31 downto 0));
+end entity;
+
+architecture a of sgn is
+  signal v32 : signed(31 downto 0);
+  signal v2 : signed(1 downto 0);
+begin
+    v2 <= to_signed(1, 2);
+    o1 <= std_logic_vector(v2);
+
+    v32 <= resize(to_signed(-5, 8), 32);   -- <<<<<<< HERE
+    o2 <= std_logic_vector(v32);
+end;
diff --git a/testsuite/synth/issue1531/tb_sgn.vhdl b/testsuite/synth/issue1531/tb_sgn.vhdl
new file mode 100644
index 000000000..8e12ae9c7
--- /dev/null
+++ b/testsuite/synth/issue1531/tb_sgn.vhdl
@@ -0,0 +1,23 @@
+entity tb_sgn is
+end tb_sgn;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sgn is
+  signal o1 : std_logic_vector(1 downto 0);
+  signal o2 : std_logic_vector (31 downto 0);
+begin
+  ent_1: entity work.sgn
+    port map (
+      o1 => o1,
+      o2 => o2);
+
+  process
+  begin
+    wait for 1 ns;
+    assert o1 = "01" severity failure;
+    assert o2 = x"ffff_fffb" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1531/tb_uns.vhdl b/testsuite/synth/issue1531/tb_uns.vhdl
new file mode 100644
index 000000000..a5e96313b
--- /dev/null
+++ b/testsuite/synth/issue1531/tb_uns.vhdl
@@ -0,0 +1,23 @@
+entity tb_uns is
+end tb_uns;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_uns is
+  signal o1 : std_logic_vector(1 downto 0);
+  signal o2 : std_logic_vector (31 downto 0);
+begin
+  ent_1: entity work.uns
+    port map (
+      o1 => o1,
+      o2 => o2);
+
+  process
+  begin
+    wait for 1 ns;
+    assert o1 = "01" severity failure;
+    assert o2 = x"0000_0003" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1531/testsuite.sh b/testsuite/synth/issue1531/testsuite.sh
new file mode 100755
index 000000000..e272f919a
--- /dev/null
+++ b/testsuite/synth/issue1531/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb uns
+synth_tb sgn
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1531/uns.vhdl b/testsuite/synth/issue1531/uns.vhdl
new file mode 100644
index 000000000..5987a81cc
--- /dev/null
+++ b/testsuite/synth/issue1531/uns.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uns is
+  port (
+    o1 : out std_logic_vector(1 downto 0);
+    o2 : out std_logic_vector (31 downto 0));
+end entity;
+
+architecture a of uns is
+  signal v32 : unsigned(31 downto 0);
+  signal v2 : unsigned(1 downto 0);
+begin
+    v2 <= to_unsigned(1, 2);
+    o1 <= std_logic_vector(v2);
+
+    v32 <= resize(to_unsigned(3, 2), 32);   -- <<<<<<< HERE
+    o2 <= std_logic_vector(v32);
+end;
-- 
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